JPH02133682U

JPH02133682U -

Info

Publication number: JPH02133682U
Application number: JP4168589U
Authority: JP
Priority date: 1989-04-11
Filing date: 1989-04-11
Publication date: 1990-11-06

Description

[Brief explanation of drawings]

第１図ａはこの考案の一実施例を示す回路図、
第１図ｂはその回路動作の真理値を示す図、第１
図ｃはテスト制御端子Ａ，Ｂ，Ｃ，Ｄ等の論理を
示す図、第２図は本考案のデコード手段と比較す
るための参考図、第３図ａは本考案の他の実施例
を示す回路図、第３図ｂはその回路動作の真理値
を示す図、第４図乃至第６図はそれぞれ従来の半
導体集積回路図である。図において、１は出力端子、２及び２２はトラ
イステート出力回路、３及び２３は第１及び第３
のテスト制御回路、４及び２４は第２及び第４の
テスト制御回路、５及び２５はデコード手段であ
る。 Figure 1a is a circuit diagram showing an embodiment of this invention;
Figure 1b is a diagram showing the truth value of the circuit operation.
Figure c is a diagram showing the logic of test control terminals A, B, C, D, etc., Figure 2 is a reference diagram for comparison with the decoding means of the present invention, and Figure 3 a is a diagram showing another embodiment of the present invention. FIG. 3B is a diagram showing the truth values of the circuit operation, and FIGS. 4 to 6 are diagrams of conventional semiconductor integrated circuits. In the figure, 1 is an output terminal, 2 and 22 are tri-state output circuits, and 3 and 23 are first and third output terminals.
4 and 24 are second and fourth test control circuits, and 5 and 25 are decoding means.

補正平１．７．１８図面の簡単な説明を次のように補正する。明細書第２０頁第１５行「第１図ａ」を、「第
１図」と補正する。明細書第２０頁第１６行「第１図ｂ」を、「第
２図」と補正する。明細書第２０頁第１６〜１７行「第１図ｃ」を
、「第３図」と補正する。明細書第２０頁第１８行「第２図」を、「第４
図」と補正する。明細書第２０頁第１９行「・・するための参考
図、第３図ａは」を、「・・するための回路図、
第５図は」と補正する。明細書第２０頁第２０行「第３図ｂ」を、「第
６図」と補正する。明細書第２１頁第１行「第４乃至第６図」を、
「第７乃至第９図」と補正する。Amendment 1.7.18 Hei 1. The brief description of the drawing is amended as follows. "Fig. 1 a" on page 20, line 15 of the specification is amended to read "Fig. 1.""Fig. 1 b" on page 20, line 16 of the specification is corrected to "Fig. 2." On page 20 of the specification, lines 16-17, "Fig. 1 c" is corrected to "Fig. 3." ``Figure 2'' on page 20, line 18 of the specification has been replaced with ``Figure 4''.
Correct it to "Fig." Page 20 of the specification, line 19, ``Reference diagram for..., Figure 3 a'' is changed to ``Circuit diagram for...''
Figure 5 is corrected as ``. "Fig. 3 b" on page 20, line 20 of the specification is corrected to "Fig. 6." The first line of page 21 of the specification “Figures 4 to 6”
Corrected to "Figures 7 to 9."

Claims

[Claims for Utility Model Registration] (1) It has an AND gate into which signals from the first and second test-dedicated terminals are input, and outputs the signal obtained by the AND gate.
and a decoding means for inputting the signal from the second test-dedicated terminal and outputting it as is; a first NAND gate to which the output signal from the internal logic circuit and the output signal from the AND gate of the decoding means are input; The output signal of the first NAND gate and the first
a first test control circuit comprising: a second NAND gate to which a signal from a test-dedicated terminal is input; and a control signal from the internal logic circuit and an output signal from the AND gate of the decoding means are input. a third NAND gate; a third NAND gate;
a second test control circuit comprising a fourth NAND gate to which the output signal of the gate and a signal from the second test dedicated terminal via the decoding means are input; and a second test control circuit of the first test control circuit. The output signal from the NAND gate of the second test control circuit is input as an input signal, the output signal of the fourth NAND gate of the second test control circuit is input as a control signal, and the control signal is set to H.
1. A MOS type semiconductor integrated circuit comprising a tri-state output circuit that outputs an input signal when the control signal is at the L level and becomes high impedance when the control signal is at the L level. (2) It has an OR gate into which signals from the first and second test-dedicated terminals are input, and outputs the signal obtained by the OR gate, and outputs the signal from the first and second test-dedicated terminals. a first NOR gate to which an output signal from an internal logic circuit and an output signal from an OR gate of the decoding means are input; and an output of the first NOR gate. a second NOR to which the signal and the signal from the first test-dedicated terminal via the decoding means are input;
a third test control circuit comprising a gate; a third NOR gate to which a control signal from the internal logic circuit and an output signal from the OR gate of the decoding means are input; and an output of the third NOR gate. a fourth N to which the signal and the signal from the second test-dedicated terminal via the decoding means are input;
a fourth test control circuit consisting of an OR gate; and an output signal from the second NOR gate of the third test control circuit is input as an input signal;
The output signal of the fourth NOR gate of the test control circuit is input as a control signal, and when the control signal is at L level, the input output signal is output, and when the control signal is at H level, it is a high impedance. 1. A MOS semiconductor integrated circuit comprising a tri-state output circuit.