JPS6198011A - Circuit for delay - Google Patents

Abstract

PURPOSE:To increase a delay time by coupling plural P channel MOS transistors (TR) and N channel MOSTRs of a CMOS gate array LSI in series. CONSTITUTION:When a unit cell of the CMOS gate array LSI is constituted, lines 2 and 7 are connected in common and lines 3 and 5 are also connected in common; and a line 4 is connected to a power source and a line 8 is grounded to constitute such an inverter that plural P channel MOSTRs Q1 and Q2 and N channel MOSTRs Q3 and Q4 are connected in series by using the unit cell. This connection constitution increase the wiring capacity of the inverter, so the quantity of delay of a unit inverter increases. Further, one inverter is composed of the LSI unit cell, so there is no decrease in the degree of freedom of wiring except a delay circuit, and the power consumption is further reduced.

Description

Detailed Description of the Invention (Industrial Application W) This invention relates to delay circuits, particularly CMOS gate arrays LS.
Regarding the delay circuit in I.

(Prior Art) FIG. 2 shows a transistor circuit diagram of a unit cell of a conventional CMOS gate array LSI. Here, Ql is a P-channel MO8) transistor whose source is connected to line 1, drain is drawn out as line 2, and gate is connected to line 3, and Q2 is a transistor whose source is connected to line 1,
It is also a P-channel MOS transistor whose drain is drawn out as line 4 and whose gate is connected to line 5.

In addition, Q3 has its source connected to line 6, its drain drawn out as line 7, and its gate connected to line 3.
Q4 is a channel MOS transistor, and Q4 is also an N-channel MOS transistor whose source is connected to line 6, drain is drawn out as line 8, and gate is connected to line 5.
3) It is a transistor.

FIG. 3 shows an example in which two CMOS inverters are made using the unit cells shown in FIG. 2. That is, by connecting lines 2 and 7 and lines 4 and 8 in common, and further connecting line 1 to the power supply, and grounding line 6,
P-channel MOS transistor Q1 and N-channel M
O3) An inverter consisting of transistor Q3 and a P-channel MO3) A transistor Q2 and an N-channel MO
An inverter consisting of an S transistor Q4 is configured.

Conventionally, in order to form a delay circuit of, for example, 10 to 20 nS in a CMOS gate array LSI, a plurality of unit cells having the configuration shown in Fig. 3 are used to connect inverters in multiple stages of about 5 to 10 stages. 4 and 5 show the case where a delay circuit is constructed using two unit cells.

That is, in FIGS. 4 and 5, 9a is a first unit cell, which has a first inverter 10a and a second inverter 10b. Further, 9b is a second unit cell, which has a first inverter lla and a second inverter llb.

In the case of FIG. 4, the output of the first inverter 10m of the first unit cell 9a is connected to the input of the second inverter 10b of the first unit cell 9 by a wiring 12, and the output of the second inverter 10b is connected to the input of the second inverter 10b of the first unit cell 9a. is connected to the input of the second inverter llb of the second unit cell 9b by a wiring 13, and the output of the second inverter llb is connected to the input of the first inverter 11a of the second unit cell 9b by an arrangement s14.

On the other hand, in FIG. 5, the output of the first inverter 10a of the first unit cell 9a is transferred to the first inverter ll of the second unit cell 9b.
The output of the first inverter lla is connected to the input of the first unit cell 9a by a wiring 15, and the output of the first inverter lla is connected to the second inverter 10 of the first unit cell 9a.
The output of the second inverter 10b is connected to the input of the second inverter llb of the second unit cell 9b by a wiring 17.

In addition, in FIGS. 4 and 5, C12°C13,
C14, C15, C16, and C17 indicate wiring capacitances.

(Problems to be Solved by the Invention) However, the delay circuit shown in FIG. 4 has the disadvantage that the wiring 12.degree. 14 is a connection within the unit cell, and the wiring capacitance is small, so that the delay time is short. On the other hand, in the delay circuit in Figure 5, the wiring is all connections between unit cells, and the wiring capacity is larger and the delay time is larger than in Figure 4, but since the wiring is done using the wiring area, other than the delay circuit This has the disadvantage of reducing the degree of freedom in circuit wiring.

This invention was made in view of the above points, and its purpose is to increase the delay time per stage (per unit cell) of the delay circuit, reduce power consumption per stage, and It is an object of the present invention to provide a delay circuit that does not reduce the degree of freedom of circuit wiring other than the delay circuit.

(Means for solving the problem) In the present invention, in a CMOS gate array LSI,
P channel MO3) transistor and N channel M
O3) Construct a delay circuit by connecting a plurality of transistors in series.

(Function) A plurality of such delay circuits are connected in multiple stages to form a delay circuit, but the delay time is large and the power consumption is low.

(Embodiment) An embodiment of the present invention will now be described with reference to the drawings. FIG. 1 shows a delay circuit according to an embodiment of the present invention.
P-channel MO3) transistors Qll, Q12 and N-channel MO3) transistors Q13. Q14 is coupled in series. That is, the source of the P-channel MO5I transistor Qll is connected to the f4 source, while the drain of the same transistor Qll is connected to the source of the P-channel MOS transistor Q12, and the drain of this MOS transistor Q12 is connected to the N-channel MOS transistor Q13. Connected to the drain. Further, the source of this N-channel MO3) transistor Q13 is connected to the drain of the N-channel MO3) transistor Q14, and the source of this MOS) transistor Q14 is grounded. The MOS transistors Q11, Q12 . Q13. The gates of Q14 are commonly connected to the signal input terminal 21. Also, P channel MOS
drain of transistor Q12 and N-channel MO8)
A connection portion of the drain of the transistor Q13 is drawn out as a signal output terminal 22.

The delay circuit configured in this manner operates as an inverter. In addition, this delay circuit is constructed by connecting lines 2 and 7 in common, connecting lines 3 and 5 in common, and connecting line 4 to the power supply while grounding line 8 in FIG. It can be formed from the unit cells shown in FIG.

The delay circuit formed in this way is
As shown in Fig. 6 (in this figure, each delay circuit is shown using the symbol of an inverter and is given the symbol 3-1), a delay circuit is constructed by connecting a plurality of delay circuits in multiple stages. According to this delay circuit 31, the delay time per stage (per unit cell) of the delay circuit increases and the power consumption per stage decreases.

That is, in FIG. 6, C32 is the wiring capacitance between each stage (between unit cells), and the calculation result of this wiring capacitance C32 and the delay time of each delay circuit 31 is shown by a straight line a in FIG. Further, the calculation results regarding the power consumption and wiring capacitance C32 of each delay circuit 31 are shown in FIG. 8 by line IIIJL. Furthermore, in these FIGS. 7 and 8,
The calculation results for the delay time and wiring capacitance per unit cell in the conventional delay circuit, as well as the calculation results for the power consumption and wiring capacitance, are shown directly! It is shown in b.

A conventional delay circuit in that case is shown in FIG. 9, where 41 is two CMOS inverters 42 connected in series.
a, 42b, each unit cell C43 is the unit cell 41
This is the wiring capacitance between This delay circuit is the same as the delay circuit in FIG.

As is clear from FIG. 7 above, the delay circuit 31 (each stage of the delay circuit in FIG. 6) of one embodiment of the present invention
has a longer delay time than the unit cells of the conventional delay circuits shown in FIGS. 4 and 9.

Furthermore, as is clear from FIG. 8, the power consumption is lower than that of the conventional unit cell. Furthermore, according to the delay circuit 31 of the embodiment of the present invention, when connecting multiple stages, only one wire is required between the stages, so unlike the conventional circuit shown in FIG. There is no reduction in the degree of freedom.

In the embodiment of the present invention shown in FIG. 1, two P-channel MOS transistors and two N-channel MOS transistors are connected in series, but more than two P-channel MOS transistors and two N-channel MOS transistors may be connected in series.

(Effects of the Invention) As described above, according to the present invention, in a CMOS gate array LSI, a delay circuit is configured by connecting a plurality of P-channel MOS transistors and a plurality of N-channel MO3) transistors in series. The delay time per stage of the delay circuit can be increased, the power consumption per stage can be reduced, and the degree of freedom of circuit wiring other than the delay circuit can be prevented from being lowered.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the delay circuit of the present invention, FIG. 2 is a circuit diagram of a unit cell of a CMOS gate array LSI, and FIG. 3 is a circuit diagram of a CMOS inverter 2 using the unit cell of FIG. 4 and 5 are circuit diagrams showing a conventional delay circuit constructed using two unit cells configured as shown in FIG. 3, and FIG. 6 is a circuit diagram showing the invention. A circuit diagram showing a delay circuit configured by connecting delay circuits in multiple stages according to an embodiment, Fig. 7 is a characteristic diagram showing calculation results for delay time and wiring capacity, and Fig. 8 shows power consumption and wiring capacity. FIG. 9 is a circuit diagram showing a conventional delay circuit used in the calculation. Qll, Q12...P channel MOS transistor, Q13. Q14...N channel MOS transistor, 31...Delay circuit.

Claims (1)

[Claims] In CMOS gate array LSI, P channel M
A delay circuit comprising a plurality of OS transistors and a plurality of N-channel MOS transistors connected in series.