KR930005445Y1 - Decorder circuit - Google Patents

Abstract

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Description

Decoder circuit

1 is a conventional decoder logic circuit diagram.

2A and 2B are a circuit diagram of an inverter and an end gate of FIG.

3 is a decoder circuit diagram of the present invention.

* Explanation of symbols for main parts of the drawings

I ₀ -I ₇ , I ₁₁ -I ₁₂ : Inverter

PM ₀ -PM ₇ , PM ₁₄ -PM ₁₆ , PM ₂₂ , PM ₂₃ , PM ₂₆ , PM ₃₁ , PM ₃₃ , PM ₃₅ : PMOS transistor

NM ₁₀ -NM ₁₃ , NM ₁₇ , NM ₂₀ , NM ₂₁ , NM ₂₄ , NM ₂₅ , NM ₂₇ , NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ , NM ₃₇ : NMOS Transistor

The present invention relates to a decoder circuit by a CMOS integrated circuit having a large number of transistors, and in particular, by reducing the number of transistors, it is possible to reduce the design area of the chip and to reduce the circuit delay caused by a large number of transistors in the circuit design. It is about a decoder circuit.

FIG. 1 is a circuit diagram of a conventional 3X8 decoder, in which the input signals X, Y, and Z are connected to the AND gates through the inverters IV ₁ , IV ₃ , and IV ₅ , respectively. _{a 0 -A 3), (a} 0, a 1, a 4, a 5), (a 0, a 2, a 4, respectively applied to the common input terminal of the a ₆₎ as well as soon as the inverter (IV _2), ( Input of the AND gates (A ₄ -A ₇ ), (A ₂ , A ₃ , A ₆ , A ₇ ), (A ₁ , A ₃ , A ₅ , A ₇ ) again through IV ₄ , (IV ₆ ) The terminals are connected in common to each other, and the output signals D ₀ -D ₇ are outputted from the AND gates A ₀ -A ₇ to explain the operation of the conventional circuit.

The input signals (X), (Y), and (Z) are inverted in the inverters IV ₁ , IV ₃ , and IV ₅ , and then the AND gates A ₀ , A ₁ , A ₂ , A ₃ ), ( A ₀ , A ₁ , A ₄ , A ₅ ), (A ₀ , A ₂ , A ₄ , A ₆ ) are respectively applied to the input terminals and at the same time the inverters (IV ₂ ), (IV ₄ ), (IV ₆ ) It is inverted again and applied to the input terminals of the end gates (A ₄ , A ₅ , A ₆ , A ₇ ), (A ₂ , A ₃ , A ₆ , A ₇ ), (A ₁ , A ₃ , A ₅ , A ₇ ) do. Therefore, at this time the AND gate (A ₀ -A ₇₎ output signal (D ₀ -D ₇₎ of the , D ₇ = XYZ.

Therefore, when the input signals X, Y, and Z are all at low potential, the output signal of the AND gate A ₀ ( ) Is output as a high potential signal, and when the input signals X, Y, and Z are all high potentials, only the output signal D ₇ = XYZ of the AND gate A ₇ is output as a high potential signal. The relation between the output signals D ₀ -D ₇ with respect to (X, Y, Z) is shown as follows.

FIG. 2A is a detailed circuit diagram of one of the inverters IV ₁ -IV _{6 of} FIG. ₁ , in which the input signal IN is connected to the PMOS transistor PM ₀ and the NMOS transistor NMO ₀ . Commonly applied to the gate, the output signal out is output at the drain connection point of the PMOS transistor PM ₀ and the NMOS transistor NM ₀ .

FIG. 2B is a detailed circuit diagram of one of the AND gates A ₀ -A ₇ of FIG. 1, and as shown therein, the input signals A, B, and C are PMOS transistors PM ₁ ,. Common to the gates of the PM ₂ , PM ₃ and the gates of the NMOS transistors NM ₁ , NM ₂ , and NM ₃ , respectively, and common to the drains of the PMOS transistors PM ₁ -PM ₃ . The NMOS transistors NM _{1 to} NM ₃ are connected in series, and the connection points thereof are configured to output an output signal Z at the drain connection points of the PMOS transistors PM ₄ and the NMOS transistors NM ₄ . .

Therefore, in the inverter circuit, when the input signal In is at high potential, the PMOS transistor PM ₀ is turned off and the transistor NM ₀ is turned on so that the output signal out is output at a low potential and the input signal In When P is low potential, the PMOS transistor PM ₀ is turned on and the NMOS transistor NM ₀ is turned off to output the output signal out at high potential.

In the AND gate circuit, a low potential signal is input to any one of the input signals A, B, and C, and any one of the PMOS transistors PM _{1 to} PM ₃ is turned on to turn on the PMOS transistor PM. ₄ ) is turned off so that the NMOS transistor NM ₄ is turned on, so the output signal Z is output at a low potential.

As described above, the AND gate used in the conventional decoder circuit is composed of a large number of MOS transistors, so that the design area of the chip increases, and thus, the delay time of the circuit increases.

The present invention is designed to reduce the design area of the chip and shorten the circuit delay time by configuring the decoder circuit using fewer MOS transistors without using the AND gate circuit in view of the conventional problems as described above. This will be described in detail with reference to the accompanying drawings.

3 is a decoder circuit diagram of the present invention, in which the input signals A, B, and C are PMOS transistors PM ₁₄ , PM ₁₅ , PM ₁₆ , (PM ₂₂ , PM ₂₃ , PM ₂₆ ) and (PM ₃₃ , PM ₃₅ ), which are commonly applied to the gates of the NMOS transistors NM ₁₇ , NM ₂₇ , and NM ₃₇ , respectively. ), (B), and (C) are NMOS transistors (NM ₁₀ , NM ₁₁ , NM ₁₂ , NM ₁₃ ), (NM ₂₀ , NM through the inverters I ₁₁ , I ₁₂ , and I ₁₃ , respectively. ₂₁ , NM ₂₄ , NM ₂₅ ), (NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ ) are connected in common to each other, and ground is connected to the gates of the PMOS transistors PM ₀ -PM ₇ , The drains of the PMOS transistors (PM ₀ ), (PM ₁ ,) (PM ₂ ), (PM ₃ ), (PM ₄ ), (PM ₅ ), (PM ₆ ), and (PM ₇ ) NM ₁₀ , NM ₂₀ , NM ₃₀ ), (NM ₁₁ , NM ₂₁ , PM ₃₁ ), (NM ₁₂ , PM ₂₁ , PM ₃₁ ), (NM ₁₂ , PM ₂₂ , NM ₃₂ ), (NM ₁₃ , PM ₂₃ , PM ₃₃ ), (PM ₁₄ , NM ₂₄ , NM ₃₄ ), Common connections to the drains of (PM ₁₅ , NM ₂₅ , PM ₃₅ ), (PM ₁₆ , PM ₂₆ , NM ₃₆ ), (NM ₁₇ , NM ₂₇ , NM ₃₇ ), and the connection points of the inverters (I ₀ -I ₇₎ And the output signals D ₀ -D ₇ are output from the inverters I ₀ -I _{7. The} PMOS transistors PM ₀ -PM ₇ , PM ₁₄ -PM ₁₆ , PM ₂₂ , PM ₂₃ , PM ₂₆ , PM ₃₁ , PM ₃₃ , PM ₃₅ are connected to a power supply terminal VDD, and the NMOS transistors NM ₁₀ -NM ₁₂ , NM ₁₇ , NM ₂₀ , NM ₂₁ , NM ₂₄ , NM ₂₅ , NM ₂₇ , NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ , NM ₃₇ ) are connected to ground.

In addition, the NMOS transistors (NM ₁₀ -NM ₁₃ , NM ₁₇ , NM ₂₀ , NM ₂₁ , NM ₂₄ , NM ₂₅ , NM ₂₇ , NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ , NM ₃₇ ) and PMOS transistors The weights of (PM _14- PM ₁₆ , PM ₂₂ , PM ₂₃ , PM ₂₆ , PM ₂₇ , PM ₃₁ , PM ₃₃ , PM ₃₅ ) are set equal to each other, and the weights of the PMOS transistors PM _0- PM ₇ are the same. Is set equal to the sum of the NMOS transistor weights connected to the drain thereof.

Referring to the effect of the present invention configured in this way in detail as follows.

When power is applied to the power supply terminal VDD, the PMOS transistors PM _{0 to} PM ₇ become conductive. At this time, when the input signals A, B, and C are all input as low potential signals, that is, "000", the PMOS transistors PM ₁₄ and-are applied by the low potential input signals A, B, and C. PM ₁₆ ), (PM ₂₂ , PM ₂₃ , PM ₂₆ ), (PM ₃₁ , PM ₃₃ , PM ₃₅ ) are turned on, and the NMOS transistors NM ₁₇ , NM ₂₇ , and NM ₃₇ are turned off.

In addition, since the low potential input signals A, B, and C are inverted into high potential signals in the inverters I ₁₁ -I ₁₃ , respectively, the NMOS transistors NM ₁₀ -NM ₁₃ and NM ₂₀ , NM _21. , NM ₂₄ , NM ₂₅ ), (NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ ) are conducted.

Therefore, the weight of the conducting PMOS transistor PM ₀ is "3", and the weights of the conducting NMOS transistors (NM ₁₀ , NM ₂₀ , NM ₃₀ ) are also "3" and are equal to each other. the low potential signal to the input terminal of the (I ₀₎ is applied to the top and yiettara output ah classic output signal (D ₀₎ of the inverter (I _0). At this time, the weights of the conducted PMOS transistors PM ₁ and PM ₃₁ are set to "3", and the weights of the NMOS transistors NM ₁₁ and NM ₂₁ which are conducted are set to "2", and thus the input terminal of the inverter I ₁ . Since a high potential signal is applied to the output signal D ₁ of the inverter I ₁ , it is output at a low potential.

By the same principle to the input terminal of the inverter the input terminal side of the weight of the conductive PMOS transistor conduction yen is larger than the weight of the MOS transistor of the inverter (I ₂ -I ₇₎ of (I ₂ -I ₇₎ Since the high potential signal is applied, the output signals D ₂ -D ₇ are output at low potential. That is, when the input signals A, B, and C are input as "000", the output signals D ₀ -D ₇ are output as "10000000".

On the other hand, when the input signals A, B, and C are input as "001", the PMOS transistors PM ₃₁ , PM ₃₂ , and PM ₃₅ are turned off by the high potential input signal C and the Ens transistors. The NMOS ₃₇ is turned on, and since the high potential input signal C is inverted to a low potential signal in the inverter I ₁₃ , the NMOS transistors NM ₃₀ , NM ₃₂ , NM ₃₄ , and NM ₃₆ are turned off. . Therefore, the weight of the conducting PMOS transistor PM ₁ is "2" and the weight of the conducting NMOS transistors NM ₁₁ and NM ₂₁ is also "2", which is the same as the input terminal of the inverter I ₁ . The low potential signal is applied to the output signal, whereby the output signal D ₁ of the inverter I ₁ is output at high potential. And, wherein the inverter _{(I 0, I 2 -I 7} ) is larger than the weight on the input terminal side of the weight of the conductive PMOS transistor, the conduction of NMOS transistor, and the inverter _{(I 0, I 2 -I 7} ) Since a high potential signal is applied to the input terminal, the output signals D ₀ and D ₂ -D ₇ are output at a low potential. That is, when the input signals A, B, and C are input as "001", the output signals D ₀ -D ₇ are output as "01000000".

As a result, the output relation of the output signals D ₀ -D ₇ with respect to the input signals A, B, and C is shown as follows.

As described in detail above, the present invention can reduce the design area of the chip because the decoder circuit is composed of fewer MOS transistors without using the AND gate circuit, and when the output signal is output after the input signal is supplied. This can shorten the delay time.

Claims (1)

Input signals A, B, and C are gates of the PMOS transistors PM ₁₄ , -PM ₁₆ , (PM ₂₂ , PM ₂₃ , PM ₂₆ ), (PM ₃₁ , PM ₃₃ , PM ₃₅ ), and NMOS transistor _{(NM | 17), (NM} 27), (NM 37) gates each common is to be junction box as well as the inverter of the _{(I 11), (I 12} ), (I 13) to yen through respective MOS transistors Connect to the gates of (NM ₁₀ -NM ₁₃ ), (NM ₂₀ , NM ₂₁ , NM ₂₄ , NM ₂₅ ) and (NM ₃₀ , NM ₃₂ , NM ₃₄ , NM ₃₆ ) in common and ground the gate The drain of the MOS transistors PM ₀ , PM ₁ , (PM ₂ ), (PM ₃ ), (PM ₄ ), (PM ₅ ), (PM ₆ ), and (PM ₇ ) is transferred to the MOS transistor (NM _10). , NM ₂₀ , NM ₃₀ ), (NM ₁₁ , NM | ₂₁ , PM ₃₁ ), (NM ₁₂ , PM ₂₂ , NM ₃₂ ), (NM ₁₃ , PM ₂₃ , PM ₃₃ ), (PM ₁₄ , NM ₂₄ , NM ₃₄ ), (PM ₁₅ , NM ₂₅ , PM ₃₅ ), (PM ₁₆ , PM ₂₆ , NM ₃₆ ), (NM ₁₇ , NM ₂₇ , NM ₃₇ ) drains and inverters (I ₀ ), (I ₁ ), ( _{I 2), (I 3)} , (I 4), (I 5), (I 6), the inverter (I ₀ -I ₇ and each connected in common to the input terminal, of the (I ₇₎₎ Up output signal (D ₀ -D ₇₎ is a decoder circuit, characterized in that is configured to be output.