JPH04341010A - Logic circuit - Google Patents

Abstract

PURPOSE:To realize the logic circuit whose number of MOS transistors(TRs) is decreased more than that of a conventional logic circuit. CONSTITUTION:When either of two input signals is logical '1', a p-channel MOS TR M1 or M2 is turned on, a N-channel MOS TR M3 or M4 is turned on. In this case, a P-channel MOS TR M5 with a high impedance is connected to an intermediate node N1 and a potential at the intermediate node N1 is lower than a logic threshold level of an inverter I1, then a level '1' is outputted to an output terminal OUT. Thus, an exclusive OR logic is obtained. Thus, number of MOS TRs is reduced and the occupied area of the logic circuit in the semiconductor integrated circuit is reduced.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit composed of a MOS type semiconductor circuit.

0002

2. Description of the Related Art FIG. 3 is a circuit diagram showing a conventional exclusive OR logic circuit. The two input ends of the NOR gate 1 are connected to input terminals IN1 and IN2, respectively. The AND gate 2 has its two input terminals connected to the input terminal IN.
1, is connected to IN2. The NOR gate 3 has its two input terminals connected to the output terminal of the NOR gate 1 and the AN
It is connected to the output terminal of D gate 2. And N.O.R.
The output terminal of gate 3 is connected to output terminal OUT.

In the logic circuit configured as described above, when only one of the two input signals input to the input terminals IN1 and IN2 is "1", the output terminal OU
When "1" is output to T and the two input signals input to input terminals IN1 and IN2 are the same, output terminal O
“0” is output to UT.

FIG. 4 is a circuit diagram showing a conventional logic circuit for obtaining an inverted output of exclusive OR. Two input terminals of the NAND gate 4 are connected to input terminals IN1 and IN2, respectively. The two input ends of the OR gate 5 are connected to the input terminals IN1 and IN2, respectively. NAN
The two input terminals of the D gate 6 are connected to the NAND gate 4, respectively.
and the output end of the OR gate 5. The output terminal of the NAND gate 6 is connected to the output terminal OUT.

[0005] The logic circuit configured as described above outputs "" to the output terminal OUT when only one of the two input signals input to the input terminals IN1 and IN2 is "1".
0" is output, and when the two input signals input to the input terminals IN1 and IN2 are the same, "1" is output to the output terminal OUT.

[0006]

[Problems to be Solved by the Invention] However, when the above-mentioned conventional logic circuit is configured with a CMOS circuit,
10 MOS transistors (5 N-channel MOS
transistor and five P-channel MOS transistors). Therefore, there is a problem that the area occupied by the logic circuit within the semiconductor integrated circuit increases. In particular, in a circuit that determines whether certain data is an even number or an odd number, the exclusive OR or its inverted output is often used, so the area occupied by the logic circuit becomes extremely large.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a logic circuit that can reduce the number of MOS transistors compared to the prior art.

[0008]

[Means for Solving the Problems] A logic circuit according to the present invention has a first circuit connected in series between a power supply terminal or a ground terminal and an intermediate junction, and whose gates are respectively connected to first and second input terminals. first and second MOS transistors of conductivity type, the sources of which are connected to the first input terminal and the gates of which are connected to the second input terminal;
a third MOS transistor of a second conductivity type, whose source is connected to the second input terminal, whose gate is connected to the first input terminal, and whose drain is connected to the intermediate junction; a fourth MOS transistor of a second conductivity type connected to the intermediate junction; an inverting circuit connected between the intermediate junction and the output terminal; and a gate whose source is connected to the power supply terminal or the ground terminal. and a fifth MOS transistor of a first conductivity type connected to the output terminal and having a drain connected to the intermediate junction.

[0009]

[Operation] In the present invention, for example, by using a high impedance MOS transistor as the fifth MOS transistor, the impedance when looking from the intermediate junction to the first input terminal side or the second input terminal side can be changed to the fifth MOS transistor. The impedance of the intermediate junction is set to be sufficiently smaller than the impedance of the MOS transistor, and the potential of the intermediate junction is set to be lower than the logic threshold of the inverting circuit when either the third or fourth MOS transistor is in an ON state. In this case, the first and second
If only one of the two input signals input to the input terminal is "1", the first or second MOS transistor will be in the ON state, and the third or fourth MOS transistor will be in the ON state. Therefore, the potential at the intermediate junction does not exceed the logic threshold of the inversion circuit. On the other hand, if the two input signals input to the first and second input terminals are the same, the first and second MOS transistors or the third and fourth MOS transistors are in the ON state. The potential at the intermediate junction exceeds a logic threshold of the inversion circuit. Therefore, when the first and second MOS transistors are connected between the power supply terminal and the intermediate node, an exclusive OR can be obtained from the output terminal, and the first and second MOS transistors can be connected between the power supply terminal and the intermediate node. When connected between the ground terminal and the intermediate node, an inverted output of the exclusive OR can be obtained from the output terminal.

According to the present invention, the inverting circuit has two M
When configured with OS transistors, a total of 7 M
A logic circuit can be constructed using OS transistors. Therefore, the number of MOS transistors used in the logic circuit can be reduced compared to the conventional technology. Thereby, the area occupied by the logic circuit within the semiconductor integrated circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

[0011]

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a logic circuit according to a first embodiment of the present invention. P-channel MOS transistors M1 and M2 are connected in series between power supply terminal VCC and intermediate node N1, and the gates of these P-channel MOS transistors M1 and M2 are connected to input terminal IN1, respectively.
, IN2. The N-channel MOS transistor M3 has its source connected to the input terminal IN1, its gate connected to the input terminal IN2, and its drain connected to the intermediate node N1. N-channel MOS transistor M4 has its source connected to input terminal I.
N2, its gate is connected to the input terminal IN1, and its drain is connected to the intermediate node N1. The inverter (inversion circuit) I1 has its input terminal connected to the intermediate junction N1, and its output terminal connected to the output terminal OUT. High impedance P channel MOS
The transistor M5 has its source connected to the power supply terminal VCC, its gate connected to the output terminal OUT, and its drain connected to the intermediate node N1. In this embodiment, the impedance when looking from the intermediate junction N1 to the input terminal IN1 side or the input terminal IN2 side is set to O by the P-channel MOS transistor M5.
The impedance is set to be sufficiently lower than the impedance when it is in the N state, and the potential of the intermediate node N1 is set to be lower than the logic threshold of the inverter I1 when either of the N channel MOS transistors M3 and M4 is in the ON state. has been done.

Next, the operation of the above-mentioned logic circuit will be explained. First, when the two input signals input to the input terminals IN1 and IN2 are both "0", the P channel MOS transistors M1 and M2 are turned on, and the N channel MOS transistors M3 and M4 are turned on.
Since it is in the FF state, "0" is output to the output terminal OUT. Furthermore, when the two input signals input to the input terminals IN1 and IN2 are both "1", the P channel MOS transistors M1 and M2 are in the OFF state, and the N channel MOS transistors M3 and M4 are in the OFF state.
Since it is in the N state, "0" is output to the output terminal OUT.

Next, when only one of the two input signals input to the input terminals IN1 and IN2 is "1", the P channel MOS transistor M1 or M2
turns on, and the N-channel MOS transistor M
3 or M4 becomes ON state. In this case, since the potential of the intermediate node N1 is lower than the logical threshold of the inverter I1, "1" is output to the output terminal OUT.

Therefore, in the logic circuit according to this embodiment, an exclusive OR can be obtained in the same manner as the conventional logic circuit shown in FIG.

According to this embodiment, the inverter I1 is
When configured with MOS transistors, the total is 7
A logic circuit can be constructed with these MOS transistors. Therefore, the number of MOS transistors used in the logic circuit can be reduced compared to the conventional technology. Thereby, the area occupied by the logic circuit within the semiconductor integrated circuit can be reduced.

FIG. 2 is a circuit diagram showing a logic circuit according to a second embodiment of the present invention. N-channel MOS transistors M11 and M12 are connected in series between the ground terminal VSS and intermediate node N11, and the gates of these N-channel MOS transistors M11 and M12 are connected to input terminal IN1, respectively.
, IN2. The P-channel MOS transistor M13 has its source connected to the input terminal IN1, its gate connected to the input terminal IN2, and its drain connected to the intermediate node N11. P-channel MOS transistor M14 has its source connected to input terminal I.
N2, its gate is connected to the input terminal IN1, and its drain is connected to the intermediate node N11. The inverter (inverting circuit) I11 has its input terminal connected to the intermediate junction N11, and its output terminal connected to the output terminal OUT. High impedance N-channel MOS
The transistor M15 has its source connected to the ground terminal VSS, its gate connected to the output terminal OUT, and its drain connected to the intermediate node N11. In this embodiment, the N-channel MOS transistor M15 sets the impedance when looking from the intermediate junction N11 to the input terminal IN1 side or the input terminal IN2 side.
The impedance is set to be sufficiently smaller than the impedance when it is in the N state, and the potential of the intermediate node N11 is set to be lower than the logic threshold of the inverter I11 when either of the P channel MOS transistors M13, M14 is in the ON state. has been done.

Next, the operation of the above-mentioned logic circuit will be explained. First, when the two input signals input to the input terminals IN1 and IN2 are both "0", the P channel MOS transistors M13 and M14 are in the ON state, and the N channel MOS transistors M11 and M12 are in the OFF state.
Since it is in the FF state, "1" is output to the output terminal OUT. Furthermore, when the two input signals input to the input terminals IN1 and IN2 are both "1", the P channel MOS transistors M13 and M14 are turned off, and the N channel MOS transistors M11 and M12 are turned off.
Since it is in the N state, "1" is output to the output terminal OUT.

Next, when only one of the two input signals input to the input terminals IN1 and IN2 is "1", the P channel MOS transistor M13 or M1
4 turns on, and the N-channel MOS transistor M
11 or M12 is turned on. In this case, since the potential of the intermediate node N11 is lower than the logical threshold of the inverter I11, "0" is output to the output terminal OUT.

Therefore, in the logic circuit according to this embodiment, the inverted output of the exclusive OR can be obtained in the same manner as the conventional logic circuit shown in FIG. Also, in this embodiment, as in the first embodiment, the number of MOS transistors used in the logic circuit can be reduced compared to the conventional one, and the area occupied by the logic circuit in the semiconductor integrated circuit can be reduced. Can be made smaller.

[0021]

As explained above, according to the present invention, by connecting, for example, a high-impedance fifth MOS transistor to the intermediate junction, a logic circuit can be configured by the first to fifth MOS transistors and the inverting circuit. Therefore, the number of MOS transistors used in the logic circuit can be reduced compared to the conventional method. Thereby, the area occupied by the logic circuit within the semiconductor integrated circuit can be reduced, and the area of the semiconductor integrated circuit can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a logic circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a logic circuit according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a conventional logic circuit for obtaining an exclusive OR.

FIG. 4 is a circuit diagram showing a conventional logic circuit that obtains an inverted output of exclusive OR.

[Explanation of symbols]

IN1, IN2; Input terminal OUT; Output terminal N1, N11; Intermediate junction M1, M2, M5, M13, M14; P channel MOS transistor M3, M4, M11, M12, M15; N channel MOS transistor I1, I11; Inverter VCC ; Power terminal VSS; Ground terminal

Claims (1)

[Claims] 1. First and second MOS transistors of a first conductivity type connected in series between a power supply terminal or a ground terminal and an intermediate junction, and having gates connected to first and second input terminals, respectively. a third MOS transistor of a second conductivity type, the source of which is connected to the first input terminal, the gate of which is connected to the second input terminal, and the drain of which is connected to the intermediate junction; a fourth MOS transistor of a second conductivity type connected to the input terminal, having a gate connected to the first input terminal and a drain connected to the intermediate junction; and a fourth MOS transistor connected between the intermediate junction and the output terminal. It is characterized by comprising an inverting circuit and a fifth MOS transistor of a first conductivity type, the source of which is connected to the power supply terminal or the ground terminal, the gate of which is connected to the output terminal, and the drain of which is connected to the intermediate junction. logic circuit.