JPH04162822A - Tri-state buffer circuit - Google Patents

Abstract

PURPOSE:To form a high density semiconductor integrated circuit by forming the integrated circuit with one inverter, four P-channel MOS transistors(TRs) and four N-channel MOS TRs. CONSTITUTION:A control input terminal 11 is connected to each gate of P- channel MOS TRs 1, 2 and an N-channel MOS TR 7 and a data input terminal 12 is connected to each gate of N-channel MOS TRs 6, 8 and a P-channel MOS TR 3. Then the TRs 2, 7 constitute an inverter, Moreover, the source of the TR 3 is connected to a power supply 14 and the drain is connected to the drain of the TRs 1,6 and the gate of the TR 5 and also to the source of a P-channel MOS TR 4. The gate of the TR 4 is connected to the output of the inverter composed of the TRs 2, 7 and the drain is connected to the gate of an N- channel MOS TR 10. Thus, the semiconductor integrated circuit is constituted of a few TRs and the high density semiconductor integrated circuit is realized.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention provides a control signal and a data signal in which the output is set to a state value of "0", "1" or a high impedance state.
Regarding state buffer circuits.

[Prior Art] FIG. 2 is a circuit diagram showing a conventional three-state buffer circuit.

The control input terminal 26 is connected to the input terminal of the inverter 21 and the NAN
It is connected to one input end of the D circuit 22. and,
The output end of the inverter 21 is connected to one input end of the NOR circuit 23. Moreover, the data input terminal 27 is NA
It is connected to the other input terminal of the ND circuit 22 and the other input terminal of the NOR circuit 23.

The output terminal of NAND circuit 22 is connected to the gate of P channel MOS transistor 24. The source of this transistor 24 is connected to a power supply 29, and the drain is connected to an output terminal 28. In addition, the NOR circuit 23
The output terminal of is connected to the gate of an N-channel MOS transistor 25. The source of this transistor 25 is connected to ground 30, and the drain is connected to the output terminal 28.

Next, the operation of the 3-state buffer circuit configured as described above will be explained.

In FIG. 2, it is assumed that the voltage VDD is applied to the power supply 29. Control signal A input to control input terminal 26
When the state value of is "0", the output signal C of the inverter 21 and the output signal C of the NAND circuit 22 both have the state value "1".
”, so the P-channel MOS transistor 24 is turned off.

Further, since the state value of the output signal E of the NOR circuit 23 is "0", the N-channel MOS transistor 25 is turned off. Therefore, since the transistors 24 and 25 connected to the output terminal 28 are both off, the output terminal 28 is in a high impedance state regardless of the state value of the data signal B input to the data input terminal 27.

When the state value of control signal A is “1”, inverter 21
The state value of the output signal is "0".

In this case, when the state value of the data signal B input to the data input terminal 27 is "0", both the NAND circuit 22 and the NOR circuit 23 output the state value "1".
The channel MOS transistor 25 is turned on and the P channel MOS transistor 24 is turned off. Therefore,
The state value of the signal F output from the output terminal 28 becomes "0".

On the other hand, when the state value of the control signal A is "1" and the state value of the data signal B input to the data input terminal 27 is "1", both the NAND circuit 22 and the NOR circuit 23 have the state value "1". 0'', the P-channel MOS transistor 24 is turned on and the N-channel MOS transistor 25 is turned off. Therefore, the output terminal 28
The state value of the signal F output from is "1".

In this manner, in the three-state buffer circuit, when the state value of the control signal is "0", the output terminal 28 is in a high impedance state. Then, the state value of the control signal is “
1" and the state value of the data signal is "0", the state value of the output signal F is "0". Also, when the state value of the control signal is "1" and the state value of the data signal is "0", the state value of the output signal F is "0". When is "1", the state value of the output signal F becomes "1".

FIG. 3 is a circuit diagram showing a three-state buffer circuit composed only of MOS transistors. Note that this circuit diagram is obtained by replacing each logic gate of the circuit shown in FIG. 2 with a MOS transistor.

The inverter is a P channel MOS transistor 33 and N
It is composed of a channel MOS transistor 39. That is, the gates of both transistors 33 and 39 are connected to the control input terminal 43. Further, the source of the transistor 33 is connected to a power supply 46, and the source of the transistor 39 is connected to a ground 47. In this inverter, the gates of transistors 33 and 39 are the input terminals of the inverter, and transistors 33 and 39
The drain of is the output terminal of the inverter.

The NAND circuit includes P-channel MOS transistors 31.
32 and N channel MOS transistors 37 and 38. That is, the gates of transistors 31.37 are connected to data input terminal 44, and the gates of transistors 32.38 are connected to control input terminal 43. Further, the sources of the transistors 31 and 32 are both connected to the power supply 46, and the sources of the transistors 31 and 32 are connected to the power supply 46.
The drains of the transistors 32 and 32 are both connected to the drain of the transistor 37. Furthermore, transistors 37 , 38 are connected in series between the drain of transistor 32 and ground 47 . In this NAND circuit, the gates of transistors 32.38 are one input terminal, the gates of transistors 31.37 are the other input terminal, and the connection point between transistors 31.32.37 is an output terminal. This output terminal is connected to the gate of P-channel MOS transistor 36.

NOR circuit is P channel MOS transistor 34.35
and N-channel MOS transistors 40 and 41. That is, the gates of transistors 34 and 40 are connected to data input terminal 44. Further, the gates of the transistors 35 and 41 are connected to the drains of transistors 33 and 39 forming an inverter. Further, the source of transistor 34 is connected to power supply 46, and the drain is connected to the source of transistor 35. Furthermore, transistors 40 and 41 are connected in parallel and interposed between the drain of the transistor 35 and the ground 47. In this NOR circuit, the gate of transistor 35.41 is one input terminal, the gate of transistor 34.40 is the other input terminal, and the connection point between transistors 35 and 40.41 is an output terminal. This output terminal is connected to the gate of N-channel MOS transistor 42.

P-channel MOS transistor 36 and N-channel MO
The S transistor 42 is connected in series between the power supply 46 and the ground 47, and the drains of the transistors 36 and 42 are both connected to the output terminal 45.

[Problems to be Solved by the Invention] However, in the conventional three-state buffer circuit described above, at least 12 MOS transistors are required as shown in FIG. For this reason, a larger number of transistors are required, which has the disadvantage of hindering the increase in the density of semiconductor integrated circuits.

The present invention has been made in view of such problems, and includes:
It is an object of the present invention to provide a three-state buffer circuit that can be configured with fewer transistors than conventional ones and can increase the density of a semiconductor integrated circuit.

[Means for Solving the Problems] A three-state buffer circuit according to the present invention causes its output to be in a high impedance state due to a data signal input to a data input terminal and a control signal input to a control input terminal.
In a 3-state buffer circuit that has either a state value of "0" or a state value of "1", it has an inverter to which the control signal is applied to its input terminal, a power supply voltage to its source, and an output terminal to its drain. the first connected to
a first N-channel MOS transistor whose source is connected to ground and whose drain is connected to the output terminal; the control signal is applied to the gate of the first N-channel MOS transistor, and the power supply voltage is applied to the source of the first N-channel MOS transistor. a second P-channel MOS transistor whose drain is connected to the gate of the first P-channel MOS transistor; a second P-channel MOS transistor whose gate is supplied with the data signal; whose source is connected to the output terminal of the inverter; a second N-channel MOS transistor connected to the gate of the first P-channel MOS transistor;
a third P-channel MOS transistor whose gate is supplied with the data signal, whose source is supplied with a power supply voltage, and whose drain is connected to the gate of the first P-channel MOS transistor; a third N-channel MOS transistor whose source is connected to ground and whose drain is connected to the gate of the first N-channel MOS transistor; and whose gate is connected to the output terminal of the inverter and its source is connected to the gate of the first P-channel MOS transistor, and its drain is connected to the first N-channel MOS transistor.
) fourth P-channel M connected to the gate of the transistor
an OS transistor, and a fourth N-channel MOS transistor whose gate is connected to the output terminal of the inno transistor, whose source is connected to ground, and whose drain is connected to the gate of the first N-channel MOS transistor. It is characterized by having the following.

[Function] In the present invention, an inverter, a NAND
A 3-state buffer circuit is not constructed by a circuit and a NOR circuit, but is constructed by one inverter, 4 P-channel MOS transistors, and 4 N-channel MOS transistors. As a result, a 3-state buffer circuit can be configured with a smaller number of transistors than in the past.

In this case, the inverter can be constructed by interposing a P-channel MOS transistor or an N-channel MOS transistor whose gates are connected to each other and whose drains are connected to each other between the power supply and the ground. As a result, a 3-state buffer circuit can be constructed using 10 MOS transistors.

Embodiments Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a circuit diagram showing a three-state buffer circuit according to an embodiment of the present invention.

The control input terminal 11 is a P-channel MOS transistor 1,
2 and N-channel MOS) are connected to each gate of the Langistaph. Further, the data input terminal 12 is connected to each gate of an N-channel MOS transistor 8 and a P-channel MOS transistor 3.

Transistors 2 and 7 constitute an inverter. That is, the drains of transistors 2 and 7 are connected to each other. The source of transistor 2 is connected to power supply 14, and the source of transistor 7 is connected to ground 14.

The drains of transistors 1 and 6 are connected to each other and to the gate of P-channel MOS transistor 5. The source of transistor 1 is connected to power supply 14, and the source of transistor 6 is connected to the output of an inverter made up of transistors 2.7.

The source of transistor 3 is connected to power supply 14,
The drain is connected to the drains of transistors 1 and 6 and the gate of transistor 5, and the drain is connected to the drains of transistors 1 and 6 and the gate of transistor 5.
Connected to the source of the OS transistor 4. The gate of this transistor 4 is connected to the output of an inverter made up of transistors 2.7, and the drain is connected to the gate of an N-channel MOS transistor 10.

At the gate of this transistor 10, an N-channel MOS
) The drains of transistors 8 and 9 are also connected. The sources of transistors 8 and 9 are both connected to ground 15, and the gate of transistor 9 is connected to the output of an inverter made up of transistors 2 and 7.

The source of the transistor 5 is connected to the power supply 14,
The drain is connected to the output terminal 13. Further, the source of the transistor 10 is connected to the ground 15, and the drain is connected to the output terminal 13.

Next, the operation of the 3-state buffer circuit configured as described above will be explained.

First, the case where the state value of the control signal A input to the control input terminal 11 is "0" will be described. In this case, P channel MOS transistor 1.2 is turned on and N
Channel MOS) Langstav is turned off. Therefore, the state values of both the inverter output signal C and the transistor 1 output signal C become "1". As a result, transistor 4 is turned off and transistor 9 is turned on. Therefore, the state value of the signal E input to the gate of the transistor 10 becomes "O".

At this time, when the state value of the data signal input to the data input terminal 12 is "0", the transistor 3 is turned on, but the state value of the signal C applied to the drain of the transistor 3 is "0" as described above. 1'', so the signal C
The state value of does not change.

On the other hand, when the state value of the data signal is "1", the transistor 8 is turned on, but since the state value of the signal E applied to the drain of the transistor 8 is "0" as described above, the signal E The state value of does not change.

In other words, when the state value of the control signal A input to the control input terminal 11 is "0", the signal input to the gate of the transistor 5 is independent of the state of the data signal B input to the data input terminal 12. The state value of C becomes "1", and the state value of signal E input to the gate of transistor 10 becomes "O".
become. Accordingly, transistors 5 and 10 are both turned off, and output terminal 13 is placed in a high impedance state.

Next, a case where the state value of the control signal input to the input terminal 11 is "1" will be described. In this case, P channel MOS transistors 1 and 2 are turned off, and N channel MOS transistor 7 is turned on. As a result, the state value of the inverter output signal becomes "0".

The state value of data signal B input to input terminal 12 is 0"
Then, transistor 6.8 is turned off and transistor 3 is turned on.

As a result, the state value of the signal C input to the gate of the transistor 5 becomes "1". At this time, since the state value of the inverter output signal is "0", the transistor 4
turns on, and the state value of the signal E input to the gate of the transistor 10 becomes "1". Therefore, the transistor 10 is turned on, the transistor 5 is turned off, and the state value of the signal F output from the output terminal 13 becomes "0".

Furthermore, when the state value of the data signal B input to the input terminal 12 is "1", the state value of the signal applied to the source of the transistor 6 is "0", so the transistor 6
turns on, and the state value of the signal C input to the gate of the transistor 5 becomes "0". Therefore, transistor 5 is turned on. Further, transistors 3 and 4 are both off, and transistor 8 is on. Therefore, the state value of the signal E input to the gate of the transistor 10 becomes "O", and the transistor 10 is turned off. As a result, the state value of the signal F output from the output terminal 13 becomes 1'1''.

The truth table of the 3-state buffer circuit according to this embodiment is shown in Table 1 below. However, 2 indicates a high impedance state.

Table 1 The 3-state buffer circuit according to this embodiment has five P-channel MOS transistors and five P-channel MOS transistors, as shown in FIG.
N-channel MOS) transistors. Therefore, the number of elements for configuring the 3-state buffer circuit is reduced compared to the conventional one, and the density of the semiconductor integrated circuit can be increased.

[Effects of the Invention] As explained above, according to the present invention, a 3-state buffer circuit can be configured with one inverter, four P-channel MOS transistors, and four N-channel MOS transistors. MOS)
The number of transistors can be reduced, and the density of semiconductor integrated circuits can be increased even more than in the past.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing a 3-state buffer circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram showing a conventional 3-state buffer circuit, and Fig. 3 is a circuit diagram showing a conventional 3-state buffer circuit consisting only of Mo8) transistors. FIG. 3 is a circuit diagram showing a buffer circuit. 1 to 5, 24. 31 to 36: P channel MOS transistor, 6 to 10, 25. 37 to 42: N channel MOS transistor, 111 12.26, 27.4
3,44; Input terminal, 13°28.45; Output terminal, 2
1; Inverter, 22; NAND circuit, 23; NOR
Circuit applicant: NEC IG Microcomputer Systems Co., Ltd.

Claims (2)

[Claims] (1) 3 states in which the output becomes either a high impedance state, a state value “0”, or a state value “1” depending on the data signal input to the data input terminal and the control signal input to the control input terminal In the buffer circuit,
an inverter to which the control signal is applied to its input end;
a first P-channel MOS transistor whose source is supplied with a power supply voltage and whose drain is connected to the output terminal; and a first N-channel MOS transistor whose source is connected to ground and whose drain is connected to the output terminal. a second P-channel MOS transistor whose gate is supplied with the control signal, whose source is supplied with the power supply voltage, and whose drain is connected to the gate of the first P-channel MOS transistor; a second N-channel MOS transistor to which a signal is applied, whose source is connected to the output terminal of the inverter and whose drain is connected to the gate of the first P-channel MOS transistor;
an S transistor, a third P-channel MOS transistor whose gate is supplied with the data signal, whose source is supplied with a power supply voltage, and whose drain is connected to the gate of the first P-channel MOS transistor; a third N-channel MOS to which the data signal is applied, whose source is connected to ground and whose drain is connected to the gate of the first N-channel MOS transistor;
a transistor, whose gate is connected to the output terminal of the inverter, whose source is connected to the gate of the first P-channel MOS transistor, and whose drain is connected to the first P-channel MOS transistor;
a fourth P-channel MOS transistor, whose gate is connected to the output terminal of the inverter, whose source is connected to the ground, and whose drain is connected to the gate of the first N-channel MOS transistor; A fourth N-channel MO connected to the gate
A 3-state buffer circuit comprising an S transistor. (2) The three-state buffer circuit according to claim 1, wherein the inverter includes a fifth P-channel MOS transistor and a fifth N-channel MOS transistor connected in series between a power supply and ground. .