JPS61133726A - Majority decision logic circuit - Google Patents

Abstract

PURPOSE:To decrease the number of elements by giving all combinations of (N+1)/2 inputs among N inputs to a gate of an N or a P-channel MOS transistor (TR) and bringing the source of the MOSTR at the pre-stage of transfer gates connected in parallel to a power supply potential or a common potential to use drains of the post-stage in common. CONSTITUTION:An input terminal 1 is connected to gates of N-channel MOS TRs 11, 14 and gates of P-channel MOS TRs 21, 24, an input terminal 2 is connected to gates of NMOS TRs 13, 16 and PMOS TRs 23, 26 and an input terminal 3 is connected to gates of NMOS TRs 15, 12 and PMOS TRs 25, 22. The NMOS TRs 11 and 12, 13 and 14, 15 and 16 constitute respectively transfer gates and PMOS TRs 21 and 22, 23 and 24, and 25 and 26 constitute respectively transfer gates. Through the constitution above, an output corresponding to the combinations of an input level inputted to input terminals 1-3 is obtained. Thus, a 3-input majority decision circuit is formed by the 7 NMOS TRs and the 7 PMOS TRs in total.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a majority circuit in a CMO8 semiconductor integrated circuit.

(Prior art) Three-man power majority circuit (rcMO8 application circuit and troubleshooting) as a means to improve the reliability of signal processing in LSI electronic circuits, written by Masaru Sugi, published by CQ Publishing Co., Ltd., November 5th edition, 1955.
PP182-184) may be used. In this method, for example, a certain signal is transmitted on three signal lines, and on the receiving side, the signals on the three lines are passed through a majority decision circuit, and the signal with the largest number of inputs is obtained as the output.

Conventionally, this three-person majority voting circuit has a configuration as shown in Figure 4, consisting of four NAND gates IA to ID, and in the case of a complementary MO8, nine P-channel MO8) run rasters, and an N-channel MOS transistor. Nine transistors were required for a total of 18 transistors.

(Problems to be Solved by the Invention) As described above, the conventional majority circuit has a large number of elements, which increases the area of the elements and increases the number of manufacturing steps.

This invention solves the problems of the above-mentioned prior art.
The present invention provides a majority logic circuit which solves the problem of a large number of elements, which hinders reduction of the element area.

(Means for Solving the Problems) This invention provides a majority logic circuit in which N+1 human power (N is an odd number) is used. Connect all the input combinations to the gates of N-channel MOS transistors or P-channel MOS transistors, and connect the drains and sources of these N-channel MOS transistors or the drains and sources of P-channel MOS transistors in series in two stages. A plurality of transformer 7 agates are connected in parallel, and an N-channel MOS is installed in front of each transformer 7 agate.
The source of the transistor or the P-channel MOS transistor is set to the power supply potential or the ground potential, and the drain of each subsequent N-channel MO3) run lister is made common.

(Function) According to the present invention, since the majority logic circuit is configured as described above, each N-channel MOS transistor of the first transformer 7 agate group and each P-channel MOS transistor of the second transformer 7 agate group By applying "HJ level" and "L" level signals to the gates, they are turned on or off, and transmitted to the output side to output the largest number of inputs to perform majority voting.

(Example) Hereinafter, an example of the majority logic circuit of the present invention will be described based on the drawings. FIG. 1 is a circuit diagram of one embodiment. In this FIG. 1, the numbers 1 to 3 are respectively
This is the third input terminal. Further, 11 to 16 are N-channel MOS transistors forming the first transformer 7 agate group, and 21 to 26 are P-channel MOS transistors forming the second transformer 7 agate group.

The first input terminal 1 is an N-channel MOS transistor 1
1.14 and the gate of P-channel MOS transistor 21.24, the second input terminal 2 is connected to the gate of N-channel MO8) range nut 13.16 and the gate of P-channel MOS transistor 23.26, The third input terminal 3 is an N-channel MO8
) Langinuta 15.12 gate and P channel M
Connected to the gates of OS transistors 25 and 22.

The sources of the N-channel MO3) run listers 11, 13, and 15 are connected to the ground terminal GND, and the drains are connected to the sources of the N-channel MOS transistors 12, 14, and 16, respectively. Thus, N-channel MOS
Transistors 11, 12, 13, 14, 15, and 16 form transfer gates, respectively.

On the other hand, P-channel MOS transistor 21°23.2
The source of 5 is connected to the power supply terminal VDDK, and each drain is connected to a P-channel MO3) range nullator 22, 2.
4.26 source.

Drains of N-channel MOS transistors 12, 14, 16 and P-channel MOS transistors 22.2
The drain of 4.26 is connected to the input terminal 4 of an inverter composed of an N-channel MOS transistor 17 and a P-channel MOS transistor 27. Thus, P-channel/channel MOS transistors 21 and 22.23
and 24, 25 and 26 form a transformer 7 agate, respectively. Note that 5 is an output terminal of the inverter.

Next, the operation of the majority logic circuit of the present invention constructed as described above will be explained. When the HJ level is input to all of the first to third input terminals 1 to 3, the N channel MOS transistors 11 to 16 are in the on state, and the P channel MO3) run listers 21 to 26 are in the off state. , rLJ is connected to input terminal 4 of the inverter.
level is added, and an "H" level appears at the output terminal 5.

Next K, when the "H" level is input to two of the three input terminals 1 to 3 (for example, the first input terminal 1 and the second input terminal 2 are "H" level) '' level, the third input terminal 3 is at rLJ level), N-channel MOS transistors 11, 13, 14.16 and P-channel MOS) run listers 22, 25 are on, N-channel MOS) run listers 12, 15 and P
Channel MOS) Run lister 21.23, 24°26
is in the off state, the input terminal 4 of the inverter is supplied with "L" through the N-channel MOS transistors 13 and 14.
'' level is added, and the ``HJ level'' also appears at the output terminal 5.

Next, the first input terminal l and the third input terminal 3 are connected to “H”.
” level and the second input terminal 2 is at the “L” level,
Similarly, when the second and third input terminals 2.3 are at the "H" level and the first input terminal 1 is at the rLJ level, the "H, J level" appears at the output terminal 5VC.

Next, when the "H" level is input to only one of the three input terminals 1 to 3 (first to third input terminals 1 to 3),
- As an example, consider the case where the first input terminal 1 is at "H" level and the second input terminal 2 and third input terminal 3 are at "L" level), N-channel MOS transistor 11.14
and P-channel/channel MOS transistor 22.23.2
5.26 is in the on state, and the N-channel MOS) run listers 12.13, 15.16 and the P-channel MOS transistor 21.24 are in the off state. When HJ level is added, its output terminal 5
The rLJ level appears.

In addition, when the rLJ level is input to all three input terminals of the first to third input terminals 1 to 3, the N channel MOS transistors 11 to 16 are in the off state, and the P channel MOS transistors 21 to 26 are in the off state. Since the inverter is in the on state, the "HJ level" is applied to the input terminal 4 of the inverter, and the "L" level appears at the output terminal 5 thereof.

From the above results, the relationship between the levels of the first to third input terminals 1 to 3 and the level of the output terminal 5 is as shown in Table 1 below. 1 total of 7 P-channel MOS transistors
You can see that it can be achieved with 4 pieces.

Table 1 In addition, FIGS. 2 and 3 respectively show other embodiments of the present invention, and FIG. In FIG. 3, a three-person majority decision circuit is constructed with six P-channel MOS transistors 41 to 46 and a pull-up resistor R2.

Among these, in FIG. 2, the first input terminal 1t is connected to the gates of N-channel MOS transistors 31 and 34,
The second input terminal 2 is connected to an N-channel MOS transistor 3.
3. Connect to the gate of 36, further K, the third input terminal 3
is connected to the gates of N-channel MOS transistors 32 and 35.

The terminals of the N-channel MOS transistors 31, 33° 35 are connected to the power supply terminal, and the drains of the N-channel MOS transistors 31, 33° 35 are connected to the N-channel MOS transistors 31, 33° 35.
The sources 7 of channel MOS transistors 32, 34, and 36 are connected to each other. This N channel MOS
) The drains of the run listers 32, 34, 36 are connected to the input terminal 4 of the inverter and are also grounded via a pull-up resistor R1.

When "H" level is applied to the first to third gates of these N-channel MOS) run listers 31 to 36, they are turned on, and when "L" level is applied, they are turned off, and these first to third gates are turned on. By applying a suitable combination of "H" level and "L" level to the input terminals 1 to 3, the circuit operates as a three-person majority voting circuit in the same manner as in the above embodiment.

In the case of FIG. 3, the first input terminal 1 is connected to the gates of P-channel MOS transistors 41 and 44,
The second input terminal 2 is a P-channel MOS transistor 4
The third input terminal 3 is connected to the gate of a P-channel MOS transistor 42.45.

The sources of P-channel MOS transistors 41, 43, 45 are grounded, and the drains thereof are connected to the sources of P-channel MOS transistors 42, 44, 46, respectively.
The drain of is connected to the input terminal 4 of the inverter, and is also connected to the power supply terminal via a pull-up resistor R2.

In this third case, when the HJ level is applied to the first to third input terminals 1 to 3, the rL
When the J level is applied, it turns on, and by appropriately combining them, it operates as a three-person majority voting circuit.

Note that in the majority logic circuit of the present invention, the inverter can be logically omitted by replacing the ground potential and the power supply voltage.

However, in this case, when the output level is "H", it decreases, and when it is rLJ, it increases.

In each of the above embodiments, an example of three-manpower is shown, and conventional one
What used to be 8 transistors can be configured with 14, and with more people, for example, 62 transistors.

(Effects of the Invention) As described above in detail, according to the present invention, all of the combinations of □ inputs out of N+1N inputs are connected to the gate of an N-channel or P-channel MOS transistor. A plurality of transfer gates in which the drains and sources of two N-channel MOS transistors or P-channel MOS transistors are connected in series are connected in parallel, the source of the first stage is set to the power supply potential or ground potential, the drain of the second stage is set to common, and the gate is connected to the gate. The input signal of "L" level or "H" level is transmitted and the majority decision t-
Since the number of transistor elements is taken, the number of transistor elements can be reduced to t-width.

Accordingly, it becomes possible to reduce the number of manufacturing steps and the element area.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of one embodiment of the majority logic circuit of the present invention, FIGS. 2 and 3 are circuit diagrams of other embodiments of the majority logic circuit of the present invention, and FIG. 4 is a conventional majority logic circuit. FIG. 1...First input terminal, 2...Second input terminal, 3
...Third input terminal, 11-16, 17.31-36
...N-channel MOS transistor, 21-26°27.41-46...P-channel MOS transistor, R1, R2...Pull-up resistor. Patent Applicant: Oki Electric Industry Co., Ltd. Figure 1 1: ¥1 inlet 75 layers) 2-t2's λ crab 1 3: Bekabu Island's side 11 to 16, 17: N+Yanjinru MO5 transistor 21 ~26,27: P 4z-n LMt) S15';'s 5' Figure 2. Figure 4-1:

Claims (1)

[Claims] Out of N inputs (N is an odd number), all combinations of (N+1)/2 inputs are connected to the gates of N-channel MOS transistors or P-channel MOS transistors, and the drain and source of these N-channel MOS transistors are connected to each other. Alternatively, connect multiple transfer gates in parallel with the drains and sources of P-channel MOS transistors connected in two stages in series, and
Channel MOS transistor or P channel MO
The source of the S transistor is set to the power supply potential or grounded, and the drains of each of the subsequent N-channel MOS transistors or P-channel MOS transistors are made common, and the input with the greater number of "H" level or "L" level is taken out. Characteristic majority logic circuit.