JPS60180330A - Cmos ratio circuit and its using method - Google Patents

Abstract

PURPOSE:To attain a circuit with less number of connecting wires and power consumption and low voltage and high speed operation by providing a logical circuit whose terminal is connected to a load MOS transistor (TR) and consisting of the one conduction channel load MOS TR and an MOS TR of the opposite conduction channel and an inverter circuit. CONSTITUTION:Suppose that a control signal phi is an active high level and input signals IN1, IN2 are at a low level at first, a PMOS TRQp2 is turned on, and NMOS TRs Qn3, Qn4 are turned off, then an output signal OUT1 is at a high level and an output signal OUT2 is at a low level. When the control signal is at an inactive low level, the NMOS TRQn1 is turned off next. When the input signal IN2 reaches a high level, the NMOS TRQn4 is turned off. Since the NMOS TRQn3 is turned off, the level of the output signal OUT1 is unchanged. When the input signal IN1 reaches a high level and the NMOS TRQn3 is turned on, the level of the output signal OUT1 is lowered, the level of the output signal OUT2 is increased, the PMOS TRQp2 is turned off and the power consumption is nearly zero.

Description

TECHNICAL FIELD The present invention relates to CMOS ratio circuits and methods of using the same.

(Hakirai Technology) Generally, there are two types of insulated gate field effect transistors (hereinafter referred to as MO8T): N-channel type and P-channel type.
In a semiconductor integrated circuit (hereinafter referred to as CI'JO8) including a complementary IWOS T constructed from has been done.

Conventionally, the 0MO8 ratio circuit is an N-channel type MO8T.
(hereinafter referred to as NMO8T), P channel type MO8T (hereinafter referred to as P
It's called MO8T. ) and the gate of NMO8T, and in order to connect the same number of PMO8T'i as ρ and NMO8T instead of one load PMO8'T, approximately twice the number of connection wiring is required, and the number of elements is also increased. This results in an increase in power consumption and a decrease in operating speed.

In response, a domino circuit has been proposed that takes advantage of the low power consumption characteristics of 0MO8 and aims to achieve high speed, reduce the number of elements, and reduce the length of connection wiring. However, since this domino circuit is a dynamic circuit and has churn air, it has a narrow operating margin and cannot operate at similar width pressures.

(Objective of the invention) The object of the present invention is 1. By solving the above problems,
The object of the present invention is to provide a CMOS ratio circuit which has a small number of elements, a small number of connected wires, and a small number of power consumption, and which is capable of high-speed operation at low voltage, and a method for using the same.

(Structure of the Invention) The 0MO8 ratio circuit of the present invention is composed of one single channel type load MO8 transistor and an opposite voltage channel type MO8 transistor.
A logic circuit whose other end is connected to the ground potential of the transistor, an input of the logic circuit (iii) and the logic circuit (fiii), and an output (011) at the connection point between the OS transistor and the gate of the transistor (MO8) for the load. an inverter circuit connected to the inverter circuit and the load MO
A setting means for setting the load M and 08 transistors of the front transistors provided in at least one of the S transistors or the logic circuits 1 and 1 to the on state by a control signal; consists of containing.

Further, in the CMOS ratio circuit of the present invention, when the control signal is active, the input of the n11 logic circuit is set to a low level, and the control signal is inactive. 11j when
It consists of performing a logic computation on a logic circuit.

(Embodiments) Hereinafter, embodiments of the present invention will be described and explained with reference to the drawings.

FIG. 1 shows a first embodiment of a CMO8 ratio circuit with a misfire of 1!11.

In the embodiment of Mizui 1, the source is the power supply VD, the drain is connected to the output and IMMOU '1', and the load PMO8TQp□ and NM(JSTω'n3r Qn4
Whip connection 6: Consists of one end of PMOS T Ql)2
The other end is connected to the ground potential, and the N
Al'J 1) Circuit 1, input is logic circuit 1 and PMO8
'I' The output is connected to the connection point 4 with Qn2 and is connected to the output terminal 5 and the gate of PMO8T Qn2, respectively, and the power supply V
The MO8TQp□ and NMO8 are intermediaries between D and ground potential.
An inverter circuit consisting of TQn2, and a drain/source serving as a setting means for setting the load PMOS TQn2 provided in this inverter circuit to a conductive state are the drains of the NMOS TQn2.

NMO8T Qnl whose source and gate are respectively connected to the control signal terminal 6. In addition, here, PMOS TQl)2 and NMO8TQn3. Qn
4 constitutes a ratio circuit. Also 2 and 3 are NAND
At the input terminal of circuit 1, each NMO8T Qnar
Connected to the gate of Qn<.

First, the operation of the embodiment of the water tester will be explained using the operation timing chart shown in FIG.

When the input signals IN, , IN2 and the control signal φ having the voltage waveforms shown in Fig. 2 are applied to the input terminal 1.2 and the control signal terminal 6, respectively, the output signals shown in Fig. 3 are applied to the connection point 4 and the output terminal 5, respectively. Output signals 0UT1 and OUT2 having the waveforms shown are output.

Initially, the control signal φ is at the active level.

When the input signals IN, , IN2 are at low level, PM
When O8TQpz is on, NMO8T Qna r
Since Qn4 is in the off state, the output signal OUT is at a high level and the output signal a0UT2 is at a low level. Next, when the control signal φ becomes an inactive low level, Nfv
108T Qn□ is turned off. Next, input signal ■
When N2 becomes high level, NMOS T Qn 4 is turned on. However, since NMOS T Qna is in the off state, the level of the output signal 0UT1 does not change. Next, the input signal IN1 becomes high level and N M O'
When S 'I' Qna turns on, the output signal OU
The level of i'l decreases, the level of output number d OUi'2 increases, and PMO8TQpz turns off. P
When MO8TQp2 is turned off, the power consumption of the circuit shown in FIG. 1 becomes almost zero.

When the starvation number φ becomes the quotient level and the input signal 1° to 2 becomes the U level, N #1. O.S.T.
Qnl becomes O/Jru, P MOS '1' Qp
If t and N MOS 'I' Qn i have a reasonable ratio, output number 1, 0UT2, however, becomes a level.
The output signal OUT 1 becomes the l-cut bell.

Further, even if the power of either the input signal IN1 or IN2 becomes high level, the output signal 0UT1 does not change, and the output signal C1[J'I'2 also does not change.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. Figure 2 removes the NMO8T Qnx in Figure 1 and replaces it with P
The source of MO8TQp3 is connected to the power supply VD, the drain to the connection point 4, and to the gate control value] signal terminal 6'.

Next, the operation of the embodiment of Sui-Tei 2 will be explained using the operation timing chart of FIG. 3.

First, the control signal 7 is set to an active low level, and the input signals IN1. If IN2 is also at a low level, PMO8'J
'Q, pa are on, NMO8TQn3. Since Qn4 is in the off state, the output signal 0 [JT, is at the quotient level, and the output signal 0UT2 is at the interrupt level, so PM O8T
Ql)2 is in the on state. The control signal ■ becomes an inactive high level, and the large Kaii IN2. I
When N□ reaches the quotient level, the output signal OUT becomes low level and the output signal 0UT2 becomes high level, so P
MOS T Ql[)2 is turned off. When the control signal ¥ becomes low level again and PMOS T Qpa turns on, and the output signal OUT becomes high level, the output signal OUi'2 becomes low level and PMOS T Qp2 turns on. Here, the on-resistance of PMO8TQp3 is made to be sufficiently smaller than the on-resistance of NMO8'11'Qna, Qn4.

FIG. 4 is a circuit diagram showing an embodiment of the unexploded 1st brother 3. The circuit of the embodiment of Mizui 3 is a combination of the circuits shown in FIGS. 1 and 2, and 7 is an inverter circuit. Control signal φ
, ¥ is designed to speed up PM O8T Q, T)2 by turning it on.

FIG. 5 is a circuit diagram showing a fourth embodiment of the present invention. The 1υ1 path of the fourth embodiment of the refrigerator is a modification of the circuit shown in FIG.
In place of the MOS T Qo, the gate is connected to the control No. 11, the source is connected to the output of the logic circuit 1, and the drain is connected to the output of the logic circuit 1 in the above embodiment. As shown in a) and (b), NOR
Logic circuits 1' and 1'' consisting of a circuit ((a) in the same figure) and a combination circuit ((b) in the same figure) of a NANI) circuit and a NOR circuit
Kongo can also exist. Note that IN, to IN7 are input signals.

μAs explained above, the circuits of these embodiments have one P
It consists of a channel-type load MOS transistor, a logic circuit consisting of an N-channel MOS transistor connected to it, an inverter circuit, and a small number of control MOS transistors, so the connections can be made depending on the number of elements. Score is low. In addition, since it is turned on at the same time as the load transistors M and 08 and is controlled so that no current flows between the power source VD and the ground potential, power consumption is low and low voltage is used.

Further, according to the CMOS ratio circuit and method of using the same of the present invention, the control signal causes the output signal 0UT2 to be at a low level for a certain period of time, and the input signal IN must also be at a low level during that period. However, for this purpose, logical operations are performed in a ratio circuit from the quotient level to a low level, using only high-speed switching states, and propagating one after another like a domino circuit. It can be configured by connecting two or more of them and using the above working force 'F1i.

Furthermore, the CMOS ratio circuit of the present invention requires fewer transistors per input terminal as the number of transistors in the logic circuit increases.

The instruction processing speed can be increased by reducing the number of gate stages when used in circuits with less regularity, such as PL8, or LSIs in which multiple input gates are often repeated.

(Effects of the Invention) As explained above in detail, the CMOS ratio circuit of the present invention and its method of use have the above structure, which reduces the number of elements, the number of connected wires, and the consumed power, and operates at high speed at low voltage. A CMOS ratio circuit and its usage method are obtained.

[Brief explanation of the drawing]

Figures 1 and 2 show the first CM and OS ratio circuit of the present invention.
．． The second embodiment is a circuit diagram showing an example, FIG. 3 is an operation timing chart thereof, and FIGS. 4 and 5 are CMOs of the present invention.
The third part of the 8 ratio circuit. Circuit diagram showing the fourth embodiment, No. 6
Figures (a) and (b) are circuit diagrams showing examples of logic circuits used in these embodiments. box. Child, 7...Inverter, IN, IN1~I
N7... Input signal, 0UT1, 0UT2...
...Output signal, Qpt-Qpa...P-channel MOS transistor, Qnt-Qns...
N-channel MOS transistor, VD...power supply, φ, 7...control signal. Abduction Hayabusa 2 times λ 乎5 pieces v-4 edition

Claims (2)

[Claims] (1) a logic circuit consisting of one conductive channel type load MOS transistor and an opposite conductive one channel type MOS transistor, one end of which is connected to the load transistor, and the other end of which is connected to the ground potential; An inverter circuit whose output is connected to the gate of the load MOS transistor h11 at the connection point between the logic circuit and the load MOS transistor, and the inverter circuit and the load IVI OS transistor or h11
a for the load provided on at least one side of the logic circuit;
and setting means for setting the os transistor to an on state by at least one control signal. (2) A logic (b) path consisting of one conductive channel type load MO# transistor and an opposite conductive channel type MOS transistor, with one end connected to the load MOS transistor and the other end connected to the ground potential. and the input is Rj
An inverter circuit whose output is connected to the gate of each of the first and second load MOS transistors at a connection point with the logic ground circuit and the load MOS transistor; In the 0MO8 ratio circuit, the input of the logic circuit 1 is kept at a low level when the Mil control signal is active, and the control signal is inactive. A method of using a CMOS ratio circuit, characterized by performing logical operations in the logic circuit.