JPS58123230A - Dynamic decoder circuit - Google Patents

Abstract

PURPOSE:To eliminate a short-circuit current in an initial state by setting the initial state through a depletion type MOSFET. CONSTITUTION:The dynamic decoder shown in a figure receives address signals A1, A2, and A3 as gate inputs to an N type MOSFET and outputs an H-level signal to a node C when a synchronizing signal phi1 is at a level H, -phi is at a level L, and the address signals are all at the level H. A P channel depletion type MOSFETD charges up a node B in an initial power-up state even when the phi1 and -phi1 are at the levels H and L and at least one of the address signal is at the level L, thus performing stable level setting. Therefore, a short-circuit current never flows to an inverter E.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a complementary dynamic decoder circuit using MO8 field effect transistors.

An example of a conventional circuit is shown in FIG. This dynamic decoder uses the address signal 'l sAt s A3 tj
: Serves as a gate input of N-channel MO8FICT, and outputs H level to node C when synchronizing signal φ1 is at H level, ¥1 is at L level, and all address signals are at H level. However, in this circuit, φ1 is high in the initial state.
When the level s#I is at the L level and at least one of the address signals is at the L level, the levels of the nodes B and C become unstable, and a short circuit current flows through the inverter I. Moreover, since it is a decoder, if there are many signals to select, the number of decoders will also increase, and a large current will flow. When a large current flows, the voltage drops in a power supply with a small current supply capacity, causing noise and rough lumps, which becomes a major problem.

In order to solve these problems, the present invention provides a decoder that can set an initial state using a depression type MO8IFET.

FIG. 2 shows an embodiment of the present invention. D in FIG. 2 is a P-channel depressed type MO8LMe device in the initial state when the power is turned on. Since the inverter E is charged up, a stable level can be set, and no short-circuit current flows through the inverter E. Also, when the decoder is in the selected state, since D is a diplenon type MO8IFET, a short circuit current flows from V DD to 11, but the MO3FICT of D is to stabilize the level of node B. There is no problem because the short circuit current can be reduced by minimizing the mutual fundance β. In this way, the decoder of the present invention eliminates short-circuit current in the initial state and has the same functionality as a conventional dynamic decoder.

Furthermore, for the dynamic decoder in which the address signal is input to the P-channel MO8FIT, the short-circuit current in the initial state can be similarly eliminated by using the N-channel depletion r-type MO8FET.

[Brief explanation of the drawing]

Figure 1 shows a complementary dynamic decoder using conventional MOSFETs, where φ is a sub-signal, ¥1 is a synchronization signal s with the opposite phase of φ, A1, A2, A3 are address signals, and B is an inverter E's synchronizing signal. Input, C is the output of inverter E, D is P channel enhancement type MO8IP
It is ET. FIG. 2 shows an embodiment of the present invention, and D is a P-channel depletion type MO3IFET.The circuit after 1 is the same as that in FIG. (Applicant: Suwa Seikosha Co., Ltd., Patent Attorney Tsutomu Mogami)

Claims (1)

[Claims] 1. A complementary dynamic decoder circuit using MO8 field effect transistors (hereinafter abbreviated as MO87ICT), characterized in that an initial state is set using a depressed triple MO8 IFET.