JPS58121829A - Driving circuit - Google Patents

Abstract

PURPOSE:To drive a large capacitive load with a very low power consumption in high speed, without a DC current circuit from a power supply to ground at the output stage of a drive circuit, by setting a phase difference between input signals to two MOS transistors(TRs) of the drive circuit. CONSTITUTION:VIN is an input signal and VO is an output signal, Q1 is a P channel MOS TR and Q2 is an N channel MOS TR. A and B are signal generating circuits driving MOS TRsQ1, Q2 respectively. The phase is set so that the low potential state of the output signal B of the circuit B includes the low potential state of the output signal A of the circuit A. In setting the phase as shown in Fig. 4, the MOS TRsQ1, Q2 are not conducted at the same time, the drive circuit is limited to charging or discharge to the load capacitor for an arbitrary time.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a part of a circuit used in an integrated circuit using a field effect transistor (hereinafter abbreviated as MO8 transistor), which can drive a large capacitive load at high speed with low power. This relates to a drive circuit.

An example of a drive circuit conventionally employed in a CMO8 circuit is shown in FIG. A circuit consisting of MOS transistors Q1 and Q2 constitutes an inverting amplifier circuit, and a circuit consisting of MOS transistors Q3 and Q4 constitutes a drive circuit.

Note that Q and Q3 are P-channel MO8) transistors, and Q2 (!: Q4 is an N-channel MOS transistor.When a large capacitive load is connected to the output V, this is used to drive it at high speed. (MOS) The channel width of transistors Q3 and Q4 also increases, and the load capacitance of the inverting amplifier circuit also increases. Therefore, the output signal of the inverting amplifier circuit
q■ Yamo will also perform slow force movements.

These operating waveforms are shown in FIG. When Vyl operates slowly, MOS transistor Q3
and Q4 become conductive at the same time, and an unnecessary large current flows from the power supply vDD to the 7-s. MOS) Runstar Q
Since the gain constants of Q3 and Q4 are large, the power dissipated due to this current can account for a large portion of the total power dissipation.

Therefore, when this type of drive circuit is used, it becomes an important problem for improving the performance and increasing the capacity of integrated circuits.

The present invention is characterized by eliminating these problems by setting a phase difference between the human input signals to the two MOS L transistors of the drive circuit. The objective is to realize integrated circuits with high performance.

FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows its operating waveforms. vIN is the input signal, vo is the output signal, and Ql is P
Channel MO8) transistor, Q2 is N channel MO7)
It is an S transistor. A and B are signal generation circuits that drive MOS transistors Q1 and Q2, respectively. As shown in FIG. 4, the phases are set so that the low potential state of the output signal B of the eight circuits includes the low potential state of the output signal A of the A circuit. When the phase is set as shown in Figure 4, the MOS
With Ranjistor Q1.

Q2 is no longer conductive at the same time, and the drive circuit.

If you choose an arbitrary time, you are limited to either charging or discharging the load capacity. Therefore, the above-mentioned problem is completely eliminated, making it possible to realize a high-performance drive circuit with low power consumption. can.

FIG. 5 shows another embodiment of the present invention, in which an inverter is used as the A circuit, a delay circuit and a NOR circuit are used as the eight circuits, and the phase setting shown in FIG. 4 is specifically made possible. That is, the A circuit receives the input signal v1N by the inverter I.
as well as the leading edge of the input signal waveform (in this case,
The trailing edge (also the trailing edge) is slightly delayed (see the waveform in FIG. 3A).

In addition, in the 8th circuit, the waveform of the input signal v1N is inverted by the NOR circuit, and the leading edge of the waveform is output with almost no time delay, but the trailing edge of the waveform is delayed and outputted by the delay circuit (3rd (See waveform B in the figure). By setting the delay amount of the eight delay circuits slightly larger than the delay amount caused by the inverter I of the A circuit, the low potential state of the output signal B of the eight circuits is changed to the output signal of the A circuit as shown in FIG. The phase is set to encompass the low potential state of A, and the MOS
) Transistors Q and Q2 are never conductive at the same time.

FIG. 6 shows still another embodiment of the signal generation circuit of the present invention.
Inverter as a circuit, inverter and N as 8 circuits
An OR circuit is used and the output signal of circuit A is also used as an input signal for eight circuits. In this way, the input signals of the A circuit and the 8 circuit are not limited to the input signal v1N, but may be configured using internal signals or output signals of the AIR circuit.

In the above embodiments of the present invention, positive logic has been described, but the same can be said for negative logic.

As explained above, the present invention has the advantage that a large capacitive load can be driven at high speed with extremely low power consumption because no direct current circuit is generated from the power supply to the ground at the output stage of the drive circuit.

[Brief explanation of drawings]

FIG. 1 is a diagram for explaining a conventional drive circuit, FIG. 2 is a waveform of the potential and I of each node in FIG. 1, FIG. 3 is an embodiment of the present invention, and FIG. 5 is a diagram showing a specific example of a signal generating circuit that generates the A signal and B signal in the present invention, and FIG. 6 is a diagram showing another specific example of the signal generating circuit in the present invention. It is. vIN Input signal, v.・・・・・・
・・・・・・Output signal, vDD ・・・・・・・Power supply, ■, ・・・・・・・Current, A・・・・・・・・・
・A signal generation circuit, B...B signal generation circuit, ■...Inverter, D...
...Delay circuit. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] In an integrated circuit using field effect transistors, the source of a first field effect transistor having one channel type of N or P is used as a first power supply, and the input is connected to an output terminal and a second electric field having the other channel type. the source of the second field effect transistor to the second power supply, and the seat of the first field effect transistor to the output terminal of the first signal generating circuit; The gate of the second transistor is connected to the output terminal of the second signal generation circuit, and the first and second signal generation circuits IJ2
A driving circuit in which a human power of the circuit is connected to an input signal terminal, wherein the first signal generation circuit has an element for delaying a leading edge of an input signal waveform from the input signal terminal, and the second
The signal generation circuit has an element that delays the trailing edge of the input signal by a delay amount slightly larger than the delay amount of the first signal generation circuit, so that the first and second field effect transistors are simultaneously conductive. A drive circuit characterized in that a phase difference is set in the input signals to the field effect transistors so that there is no period during which the field effect transistors are input.