KR940000266B1 - Low power consuming output buffer circuit - Google Patents

Abstract

The low power consuming output buffer circuit is disclosed in which the output of a NOR gate is connected to the gates of a PMOS transistor and an NMOS transistor, the output of a NAND gate is connected to the gates of the PMOS and NMOS transistors, and the drain of the PMOS transistor is connected to the gate of a pull-up transistor and commonly connected to the gate of a pull-down transistor and the drain of the NMOS transistor via the PMOS transistor and NMOS transistor, thereby reducing current flowing via the output buffer.

Description

Low Power Consumption Output Buffer Circuit

1 and 3 are conventional output buffer circuit diagrams.

2 and 4 are tables of truth according to FIGS. 1 and 3;

5 and 7 show an output buffer circuit according to the present invention.

6 and 8 show the truth table according to FIGS. 5 and 7.

* Explanation of symbols for main parts of the drawings

MP ₁ , MP ₂ , MP ₄ , MP ₈ : Pull-Up Transistor

MN ₁ , MN ₂ , MN ₅ , MN ₈ : Pulldown Transistor

MP ₃ , MP ₄ , MP ₆ , MP ₇ : Pymotransistor

MN ₃ , MN ₄ , MN ₆ , MN ₇ : Enmotransistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit of an integrated circuit, and more particularly to a low power consumption output buffer circuit that enables low power consumption of an output buffer stage.

1 is a diagram of a conventional output buffer circuit, in which an enable signal A is applied to an input terminal of one side of a NAND gate N _{2 as} well as an input of a noar gate N ₃ through an inverter N ₁ . It is connected to be applied to one input terminal, the input signal (B) is connected to be applied to the other input terminal of the NAND gate (N ₂ ) and the NOR gate (N ₃ ), and the NAND gate (N ₂ ) and the NOA gate ( The output terminal of N ₃ ) is connected to the gates of the pull-up transistor (MP ₁ ) and pull-down transistor (MN ₁ ), respectively, so that the output signal is output from the drain connection point of the pull-up transistor (MP ₁ ) and pull-down transistor (MN ₁ ). do.

3 is another conventional output buffer circuit diagram, in which an enable signal A is applied to an input terminal of one side of a NAND gate N ₇ as shown therein, and a noah gate N ₅ through an inverter N ₄ . Is connected to the input terminal of one side, and the input signal (B) is connected to be applied to the other input terminal of the NAND gate (N ₇ ) and the NOR gate (N ₅ ), the NOR gate (N ₅ ) and NAND The output terminals of the gate N ₇ are connected to the gates of the pull-up transistor MP ₂ and the pull-down transistor MN ₂ through the inverters N ₆ and N ₈ , respectively, so that the pull-up transistor MP ₂ and the pull-down are connected. The output signal is output at the drain connection point of the transistor MN _2. The operation of the conventional circuit will be described with reference to the truth table in FIGS. 2 and 4.

If the enable signal A is low potential in the circuit of FIG. 1, the pull-up transistor MN ₁ is output because the high potential signal is output from the NAND gate N ₂ regardless of the input signal B by the low potential signal. Since the high potential signal is output from the inverter N ₁ by the low potential enable signal A, the low potential signal is output from the noah gate N ₃ regardless of the input signal B and pulled down. Transistor MM ₁ is turned off, so the output is in a high impedance (Z) state.

In addition, when the enable signal A has a high potential, the high potential signal is applied to one input terminal of the NAND gate N2, and is inverted into a low potential signal of the inverter N ₁ to invert the noah gate N ₃ . The output signals of the NAND gate N ₂ and the NOR gate N ₃ are determined according to the input signal B. That is, when the input signal B has a low potential, the high potential signal is output from the NAND gate N ₂ , the pull-up transistor MP ₁ is turned off, and the high potential signal is output from the NOR gate N ₃ , and the pull-down transistor is output. Since (MN ₁ ) is conducting, the output becomes low potential. In addition, when the input signal B has a high potential, a low potential signal is output from the NAND gate N ₂ , and a pull-up transistor MP ₁ is conducted, and a low potential signal is output from the NOR gate N ₃ , and a pull-down transistor MN is output. ₁ ) is off, so the output is at high potential.

The circuit of FIG. 3 also operates in the same manner as the circuit of FIG. That is, when the enable signal A is at low potential, the low potential signal is output at the noah gate N ₅ and the high potential signal is output at the NAND gate N ₇ regardless of the input signal B, thereby inverting the inverter ( N ₆₎ is a high potential signal is output, and the low potential signal by the inverter (N ₈₎ outputs, so all the pull-up transistor (MP ₂₎ and the pull-down transistor (MN ₂₎ off, the output is a high impedance (Z) state . In addition, when the enable signal A has a high potential, when the input signal B has a low potential, a high potential signal is output from the NOR gate N ₅ and the NAND gate N ₇ so that the inverter N ₆ , Since both low potential signals are output from (N ₈ ), the pull-up transistor (MP ₂ ) is turned on and the pull-down transistor (MN ₂ ) is turned off so that the output becomes high potential, and when the input signal (B) is high potential, ₅ ) and the low potential signal is output from the NAND gate (N ₇ ), and the high potential signal is output from both the inverters (N ₆ ) and (N ₈ ), so the pull-up transistor (MP ₂ ) is turned off and the pull-down transistor (MN ₂ ) is Conduction results in a low potential.

However, in the conventional circuit, the sizes of the pull-up transistors MP ₁ and MP ₂ and the pull-down transistors MN ₁ and MM ₂ are relatively larger than those of other internal transistors, and thus the NAND is output when the internal output signal is output. Pull-up, pull-down transistors (MP ₁ , MP ₂ ), (MN ₁ , MN ₂ ) when the output signals of the gate (N ₂ ) and noah gate (N ₃ ) or inverter (N ₆ ), (N ₈ ) overlap The large current flows through the circuit to reduce the performance of the integrated circuit.

In view of the above drawbacks, the present invention has been devised to reduce the power consumption by reducing the current flowing through the transistor of the output stage by operating the pull-up transistor and the pull-down transistor of the output stage of the buffer circuit without overlapping. When described in detail with reference to the drawings as follows.

5 is an output buffer circuit diagram according to the present invention, in which the enable signal A is applied to one input terminal of the NAND gate N ₁₂ as well as the noah gate N through the inverter N ₉ . ₁₀ ) is connected to be applied to one terminal of the input terminal, or the input signal (B) is connected to be applied to the other input terminal of the NOR gate (N ₁₀ ) and the NAND gate (N ₁₂ ), the NOA gate (N ₁₀ ) and NAND An output buffer circuit configured to be connected to the output terminal pull-up transistor MP ₅ and the pull-down transistor MN ₅ of the gate N ₁₂ , respectively, wherein the output terminal of the NOR gate N ₁₀ is the PMOS transistor MP. ₃ ) and the gate of the NMOS transistor MN ₃ , the output terminal of the NAND gate N ₁₂ is connected to the gate of the PMOS transistor MP ₄ and the NMOS transistor MN ₄ . The drain of the MOS transistor MP ₃ is transferred to the PMOS transistor. Register (MP ₄₎ of Sound, the NMOS transistor (MN ₃₎ of the drain and the pull-up transistor (MP ₅₎ connected in common to the gate, and the PMOS transistor (MP ₄₎ a drain, and the NMOS transistor (MN of a source of a ₃₎ configured by common-connected to the gate and drain of the NMOS transistor (MN ₅₎ of said NMOS transistor (MN _4).

FIG. 7 is another embodiment output buffer circuit diagram of the present invention, in which the enable signal A is applied to one input terminal of the NAND gate N _{15 as} well as the NOR gate N through the inverter N ₁₄ . ₁₈ is applied to one input terminal of the NAND gate, and the connection signal B is connected to be applied to the NAND gate N ₁₅ and the other input terminal of the NOR gate N ₁₈ , and the NAND gate N ₁₅ and the NOA gate are connected. An output buffer circuit in which an output terminal of (N ₁₈ ) is connected to a gate of pull-up transistor (MP ₈ ) and pull-down transistor (MN ₈ ) through inverters (N ₁₆ ) and (N ₁₉ ), respectively, wherein the inverter (N) The output terminal of ₁₆ ) is connected to the gates of the PMOS transistor (MP ₆ ) and the MOS transistor (MN ₆ ), and the output terminals of the inverter (N ₁₉ ) are the PMOS transistor (MP ₇ ) and the MOS transistor (MN). ₇ ) and a gate of the PMOS transistor MP ₆ A lane is commonly connected to the drain of the NMOS transistor MN ₆ , the source of the PMOS transistor MP ₇ and the gate of the pull-up transistor MP ₈ , and the source and PMOS transistor of the NMOS transistor MN ₆ . The drain of (MP ₇ ) is commonly connected to the drain of the MOS transistor MN ₇ and the gate of the MOS transistor MN ₈ .

The working effect of the present invention configured as described above will be described in detail with reference to the truth table in FIGS. 6 and 8.

In the circuit of FIG. 5, when the enable signal A is low potential, the high potential signal is output at the NAND gate N ₁₂ and the low potential signal is output at the NOR gate N ₁₀ regardless of the input signal B. PMO transistors MP ₃ and NMOS transistors MN ₄ are turned on, and PMO transistors MP ₄ and NMOS transistors MN ₃ are turned off, and thus pull-up transistors MP ₅ and NMOS transistors are turned off. Transistor MN ₅ is turned off, and the output is in a high impedance (Z) state.

In addition, when the enable signal A has a high potential, the high potential signal is applied to one input terminal of the NAND gate N ₁₂ , and is inverted to a low potential signal in the inverter N ₉ to be a noah gate N ₁₀ . Since it is applied to one input terminal of, output signals of the NAND gate N ₁₂ and the NOR gate N ₁₀ are determined by the input signal B. That is, when the input signal B is at low potential, the high potential signal is output from the NOR gate N ₁₀ , the PMOS transistor MP ₃ is turned off, the NMOS transistor MN ₃ is turned on, and the NAND gate ( A high potential signal is output from N ₁₂ ) so that the PMOS transistor MP ₄ is turned off and the NMOS transistor MN ₄ is turned on. Accordingly, a low potential is applied to the gate of the pull-down transistor MN ₅ so that the pull-down transistor ( The output becomes high potential because MN ₅ ) is turned off and pull-up transistor MP ₅ is conducted because the potential between the source and drain of enMOS transistor MN ₃ becomes low.

In addition, when the input signal B has a high potential, a low potential signal is output from both the NOR gate N ₁₀ and the NAND gate N ₁₂ , so that the PMOS transistors MP ₃ and MP ₄ become conductive. EnMOS transistors (MN ₃ ) and (MN ₄ ) are turned off, so that a high potential is applied to the gate of the pull-down transistor (MN ₅ ) so that the conduction is carried out, and the source and the drain of the enMOS transistor (MN ₃ ) become high potential. Since the pull-up transistor MP ₅ is turned off, the output becomes low potential.

As a result, the PMO transistors MP ₃ and MP ₄ and the NMOS transistors MN ₃ and MN ₄ effectively overlap the signals of the drain and the source of the NMOS transistor MN ₃ , thereby pulling up the pull-up transistor MP _5. And the current flowing through the pull-down transistor (MN ₅ ) can be reduced.

The circuit of FIG. 7 is also operated in the same manner as the circuit of FIG.

That is, when the enable signal A is at low potential, the high potential and low potential signals are respectively output from the NOR gate N ₁₈ of the NAND gate N ₁₅ regardless of the input signal B, and the inverter N ₁₆ is output. ), (N ₁₉ ), the low and high potential signals are output, respectively, so that PMOS transistor (MP ₆ ) and NMOS transistor (MN ₇ ) are turned on, PMO transistor (MP ₇ ) and enmo transistor (MN _6). ) Is off, and both the pull-up transistor MP ₈ and the pull-down transistor MN ₈ are off, so that the output is in the high impedance (Z) state.

In addition, when the enable signal A has a high potential, when the input signal B has a low potential, a high potential signal is output from both the NAND gate N ₁₅ and the noah gate N ₁₈ , and the inverter N _16. Since the mode low potential signal is output from (N ₁₉ ), the PMOS transistors (MP ₆ , MP ₇ ) are turned on, and the NMOS transistors (MN ₆ , MN ₇ ) are turned off, and thus the pull-up transistor (MP ₈ ) Is turned off and pull-down transistor MN ₈ is turned on so that the output is at low potential.

In addition, when the input signal B has a high potential, a low potential signal is output from both the NAND gate N ₁₅ and the NOR gate N ₁₈ , and a high potential signal is output from both the inverters N ₁₆ and N ₁₇ . The output PMO transistors MP ₆ and MP ₇ are turned off and the NMOS transistors MN ₆ and MN ₇ are turned on. Accordingly, the pull-up transistor MP ₈ is turned on and the pull-down transistor MN ₈ is turned off. The output is at high potential.

As a result, the PMOS transistors MP ₆ and MP ₇ and the NMOS transistors MN ₆ and MN ₇ effectively overlap the signals of the source and the drain of the PMOS transistor MP ₇ so that the pull-up transistor MP ₈ is applied. And a current flowing through the pull-down transistor MN ₈ may be reduced.

As described above, this emission shows that the size of the pull-up and pull-down transistors of the output stage is relatively larger than that of the transistors in the internal circuit. However, the effective operation of the output stage is achieved by reducing the current flowing through the output buffer. There are various effects, such as being able to implement a low current integrated circuit.

Claims (2)

The enable signal A is applied to one input terminal of the NAND gate N ₁₂ and is also applied to one input terminal of the NOR gate N ₁₀ through an inverter N ₉ , and an input signal B is applied to the NOA. gate (N ₁₀₎ and is connected to be applied to the other input terminal of the NAND gate (N _12), said NOR gate (N ₁₀₎ and the NAND gate pull-up transistor (MP ₅₎ and pull-down of the output terminal connected in series (N ₁₂₎ In the output buffer circuit respectively connected to the gate of the transistor MN ₅ , the output terminal of the NOR gate N ₁₀ is connected to the gate of the PMOS transistor MP ₃ and the NMOS transistor MN ₃ , An output terminal of the NAND gate N ₁₂ is connected to the gates of the PMOS transistor MP ₄ and the NMOS transistor MN ₃ , and the drain of the PMOS transistor MP ₃ is connected to the pull-up transistor MP _5. Is connected to a gate of Transistor (MP ₄₎ and NMOS transistor (MN ₃₎ the respective through low power output, characterized in that is configured to connect, in common to the drain of the gate and the NMOS transistor (MN ₄₎ of the pull-down transistor (MN ₅₎ buffer Circuit. The enable signal A is applied to one input terminal of the NAND gate N ₁₅ and is also applied to one input terminal of the NOR gate N ₁₈ through an inverter N ₁₄ , and an input terminal B is applied to the NAND. gate (N ₁₅₎ and an output terminal an inverter _{(N 16), (N 19} ) of the NOR gate (N ₁₈₎ the other end is connected to be applied to the input terminal, the NAND gate (N ₁₅₎ and NOR gate (N ₁₈₎ of the In the output buffer circuit configured to be connected to the gate of the pull-up transistor (MP ₈ ) and the pull-down transistor (MN ₈ ) of the serial connection through the connection, respectively, the output terminal of the inverter (N ₁₆ ) to the PMOS transistor (MP ₆ ) and the A gate of a MOS transistor MN ₆ , an output terminal of the inverter N ₁₉ , a gate of a PMOS transistor MP ₇ and an NMOS transistor MN ₇ , and a PMOS transistor MP _6. ) also connecting the drain to the gate of the pull-up transistor (MP ₈₎ and Ulreo low power of the NMOS transistor (MN ₆₎ and a PMOS transistor, wherein (MP ₇₎ for each through configured to commonly connected to the drain of the pull-down transistor (MN ₈₎ the gate and the NMOS transistor (MN ₇₎ of Consumption output buffer circuit.