KR920011070A - Low Power Consumption Output Buffer Circuit - Google Patents

Low Power Consumption Output Buffer Circuit Download PDF

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Publication number
KR920011070A
KR920011070A KR1019900018289A KR900018289A KR920011070A KR 920011070 A KR920011070 A KR 920011070A KR 1019900018289 A KR1019900018289 A KR 1019900018289A KR 900018289 A KR900018289 A KR 900018289A KR 920011070 A KR920011070 A KR 920011070A
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KR
South Korea
Prior art keywords
transistor
buffer circuit
power consumption
low power
gate
Prior art date
Application number
KR1019900018289A
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Korean (ko)
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KR940000266B1 (en
Inventor
박종훈
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019900018289A priority Critical patent/KR940000266B1/en
Publication of KR920011070A publication Critical patent/KR920011070A/en
Application granted granted Critical
Publication of KR940000266B1 publication Critical patent/KR940000266B1/en

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

내용 없음No content

Description

저전력 소비 출력 버퍼 회로Low Power Consumption Output Buffer Circuit

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제5도와 제7도는 본 발명에 따른 출력 버퍼 회로도, 제6도와 제8도는 각각 제5도와 제7도에따른 회로의 진리치표이다.5 and 7 are output buffer circuit diagrams according to the present invention, and Figs. 6 and 8 are truth tables of circuits according to Figs. 5 and 7, respectively.

Claims (3)

낸드게이트와 노아케이트가 두 개입력이 인버터를 거쳐 접속된 종래의 출력버퍼회로에 있어서, 풀다은트랜지스터와 풀업트랜지스터를 중첩되지 않게 배열하여 작동하도록 구성된 것을 특징으로 하는 저전력 소비 출력버퍼 회로.A conventional output buffer circuit in which two inputs of a NAND gate and a no-agate are connected through an inverter, wherein the low power consumption output buffer circuit is configured to operate by arranging a pull-down transistor and a pull-up transistor so as not to overlap each other. 상기 제1항에 있어서, 노아케이트(N10)의 출력단에 트랜지스터(MP3)와, (MN3)의 게이트를 연결하고, 낸드게이트(N12)의 출력단에 트랜지스터(MP4, MN4)의 게이트를 연결하고, 트랜지스터(MP3)의 소오스 트랜지스터(MP4)의 드레인 사이를 연결하여 트랜지스터(MN3)의 드레인과 트랜지스터(MP5)의 게이트에 접속하고, 트랜지스터(MP4)의 소오스와 트랜지스터(MN4)의 드레인을 접속하고 트랜지스터(MN3)의 소오스와 트랜지스터(MN5)의 게이트를 연결하고, 트랜지스터(MN5)의 소오스와 트랜지스터(MN5)의 드레인 사이에 입출력단을 접속하여 구성된 것을 특징으로 하는 저전력 소비 출력 버퍼 회로.According to the claim 1, wherein the transistors in the output stage of the quinoa Kate (N 10) (MP 3) and, connected to the gate of the (MN 3), and the transistor to the output terminal of the NAND gate (N 12) (MP 4, MN 4) for connecting the gate and connecting the drain of the source transistor (MP4) of the transistors (MP 3) connected to the gate of the drain of the transistor (MP 5) of a transistor (MN 3), and the source and the transistor (MP 4) connecting the drain of the transistor (MN 4) and connecting the gate of the source and the transistor (MN 5) of the transistor (MN 3) and connecting the input and output terminals to the drain of the source and the transistor (MN 5) of the transistor (MN 5) Low power consumption output buffer circuit, characterized in that configured. 상기 제2항에 있어서, 노아게이트(N10)와 낸드게이트(N12)의 출력단에 인버터(N18)(N19)를 연결하고 이에 따라 삼보형으로 작동하도록 구성된 것을 특징으로 하는 저전력 소비 출력 버퍼회로.The low power consumption output according to claim 2, wherein the inverter N 18 and N 19 are connected to the output terminals of the NOR gate N 10 and the NAND gate N 12 , and thus operate in a tribo type. Buffer circuit. ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.※ Note: This is to be disclosed by the original application.
KR1019900018289A 1990-11-13 1990-11-13 Low power consuming output buffer circuit KR940000266B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019900018289A KR940000266B1 (en) 1990-11-13 1990-11-13 Low power consuming output buffer circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900018289A KR940000266B1 (en) 1990-11-13 1990-11-13 Low power consuming output buffer circuit

Publications (2)

Publication Number Publication Date
KR920011070A true KR920011070A (en) 1992-06-27
KR940000266B1 KR940000266B1 (en) 1994-01-12

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ID=19305919

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019900018289A KR940000266B1 (en) 1990-11-13 1990-11-13 Low power consuming output buffer circuit

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KR (1) KR940000266B1 (en)

Also Published As

Publication number Publication date
KR940000266B1 (en) 1994-01-12

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