KR970078021A

KR970078021A - Exclusive Noah Gate with Three Inputs with Reduced Transistor Count

Info

Publication number: KR970078021A
Application number: KR1019960018522A
Authority: KR
Inventors: 김지영
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-29
Filing date: 1996-05-29
Publication date: 1997-12-12
Also published as: KR0161496B1

Abstract

본 발명은 트랜지스터 수가 감소된 3개 입력을 갖는 배타적 노아 게이트에 관한 것이다. 본 발명은, 제1, 제2 및 제3입력단의 신호를 인버팅하는 제1, 제2 및 제3 인버터와, 소오스에 공급전압이 접속되고 게이트에 상기 제2입력단이 접속되는 제1PMOS 트랜지스터와, 소오스에 상기 제1PMOS 트랜지스터의 드레인이 접속되고 게이트에 상기 제1입력단이 접속되는 제2PMOS 트랜지스터와, 상기 제2PMOS 트랜지스터의 드레인과 상기 제2입력단 사이에 개재되고, 게이트에 각각 상기 제1입력단 및 상기 제1인버터의 출력단이 접속되는 제1NMOS 트랜지스터 및 제3PMOS 트랜지스터로 구성되는 제1트랜스미션 게이트와, 상기 제2PMOS 트랜지스터의 드레인과 상기 제1입력단 사이에 개재되고, 게이트에 각각 상기 제2입력단 및 상기 제2인버터의 출력단이 접속되는 제2NMOS 트랜지스터 및 제4PMOS 트랜지스터로 구성되는 제2트랜스미션 게이트와, 소오스에 상기 제3입력단이 접속되고 게이트에 상기 제2PMOS 트랜지스터의 드레인이 접속되고 드레인에 최종 출력단이 접속되는 제5PMOS 트랜지스터와, 상기 제2PMOS 트랜지스터의 드레인과 상기 최종 출력단 사이에 개재되고, 게이트에 각각 상기 제3입력단 및 상기 제3인버터의 출력단이 접속되는 제6PMOS 트랜지스터 및 제3NMOS 트랜지스터로 구성되는 제3트랜스미션 게이트와, 드레인에 상기 제5PMOS 트랜지스터의 드레인이 접속되고 게이트에 상기 제2PMOS 트랜지스터의 드레인이 접속되는 제4NMOS 트랜지스터와, 드레인에 상기 제4NMOS 트랜지스터의 소오스가 접속되고 게이트에 상기 제3입력단이 접속되고 소오스에 접지 전압이 접속되는 제5NMOS 트랜지스터를 구비하는 것을 특징으로 한다. 따라서 본 발명은 종래기술과 동일한 논리기능을 수행하면서 트랜지스터 수가 17개로 감소되어 레이아웃의 면적을 감소시킬 수 있는 장점이 있다.The present invention relates to an exclusive NOR gate having three inputs with a reduced transistor count. The present invention provides a display device comprising: first, second and third inverters for inverting signals at first, second and third input terminals, first PMOS transistors having a supply voltage connected to a source and a second input terminal connected to a gate thereof; A second PMOS transistor having a source connected to the drain of the first PMOS transistor and a gate connected to the first input terminal, a second PMOS transistor connected between a drain of the second PMOS transistor and the second input terminal, respectively; A first transmission gate including a first NMOS transistor and a third PMOS transistor to which the output terminal of the first inverter is connected, and interposed between the drain and the first input terminal of the second PMOS transistor, respectively; A second transmission gate including a second NMOS transistor and a fourth PMOS transistor to which an output terminal of the second inverter is connected, and a third input terminal to a source; A fifth PMOS transistor connected to a gate thereof, a drain of the second PMOS transistor connected to a gate thereof, and a final output terminal thereof connected to a drain thereof; A third transmission gate including a sixth PMOS transistor and a third NMOS transistor connected to an output terminal of a three inverter, a fourth NMOS transistor connected to a drain of the fifth PMOS transistor, and a drain of the second PMOS transistor connected to a gate thereof; And a fifth NMOS transistor having a source connected to the fourth NMOS transistor at a drain, a third input terminal connected to a gate, and a ground voltage connected to a source. Therefore, the present invention has the advantage of reducing the area of the layout by reducing the number of transistors to 17 while performing the same logic function as the prior art.

Description

Exclusive Noah Gate with Three Inputs with Reduced Transistor Count

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명의 실시예에 따른 3개 입력을 갖는 배타적 노아 게이트의 회로도.2 is a circuit diagram of an exclusive NOR gate with three inputs in accordance with an embodiment of the present invention.

Claims

First, second and third inverters for inverting signals of the first, second and third input terminals, first PMOS transistors having a supply voltage connected to a source and a second input terminal connected to a gate thereof, and A second PMOS transistor connected between a drain of the first PMOS transistor and a first input terminal connected to a gate thereof, and interposed between the drain and the second input terminal of the second PMOS transistor, respectively, the first input terminal and the first inverter connected to a gate of the second PMOS transistor; A first transmission gate including a first NMOS transistor and a third PMOS transistor to which an output terminal of the first terminal is connected; A second transmission gate interposed between the drain of the second PMOS transistor and the first input terminal and having a second NMOS transistor and a fourth PMOS transistor connected to a gate of the second input terminal and an output terminal of the second inverter, respectively; A fifth PMOS transistor having a third input terminal connected to a source, a drain of the second PMOS transistor connected to a gate thereof, and a final output terminal connected to a drain thereof; A third transmission gate interposed between the drain of the second PMOS transistor and the final output terminal and having a sixth PMOS transistor and a third NMOS transistor connected to a gate of the third input terminal and the output terminal of the third inverter, respectively; A fourth NMOS transistor having a drain connected to the drain of the fifth PMOS transistor and a drain connected to a gate of the second PMOS transistor; And a fifth NMOS transistor having a source connected to the fourth NMOS transistor at a drain, a third input terminal connected to a gate, and a ground voltage connected to a source.

※ Note: The disclosure is based on the initial application.