KR970078011A

KR970078011A - Composite gate circuit and its design method

Info

Publication number: KR970078011A
Application number: KR1019960016392A
Authority: KR
Inventors: 이학민
Original assignee: 김광호; 삼성전자 주식회사
Priority date: 1996-05-16
Filing date: 1996-05-16
Publication date: 1997-12-12

Abstract

이 발명은 복합 게이트 회로 및 그 설계방법에 관한 것으로, 씨모스 논리 게이트 설계에서, 피형 모스 트랜지스터와 엔형 모스 트랜지스터가 직, 병렬 대칭을 이루지 않고, 피형 트랜지스터는 출력 1을 기준으로, 엔형 모드 트랜지스터는 출력 0을 기준으로하여 짓렬 모스 트랜지스터의 병렬 배열로 레이아웃을 유도하여, 간단한 설계로 정확한 타이밍 시뮬레이션을 할 수 있는 복합 게이트 회로 및 그 설계방법에 관한 것이다.The present invention relates to a composite gate circuit and a method of designing the same. In the CMOS logic gate design, a transistor having a morphotropic morphology and a morphotropic transistor having no morphology are parallel to each other, The present invention relates to a composite gate circuit and a method for designing a composite gate circuit capable of performing accurate timing simulation with a simple design by guiding a layout in a parallel arrangement of a pseudo MOS transistor on the basis of an output 0.

Description

Composite gate circuit and its design method

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is a trivial issue, I did not include the contents of the text.

제3도는 이 발명의 실시에에 따른 복합 게이트 설계방법에 의해 설계된 복합 게이트의 구성도.FIG. 3 is a block diagram of a composite gate designed by a composite gate design method according to an embodiment of the present invention; FIG.

Claims

In the CMOS logic gate design, the mos transistor and the n-type MOS transistor do not form a direct and parallel symmetry, and the transistors to be mapped form the output 1 and the MOS transistors of the n-type form a layout in parallel arrangement of the mos transistor A method for designing a composite gate.

A fourth PMOS transistor pmos_9 connected in parallel to the third PMOS transistor pmos_8, a fifth PMOS transistor pmos10 connected in parallel to the first PMOS transistor pmos_6, a second PMOS transistor pmos7 connected in parallel, And the sixth PMOS transistor pmos_11 are connected in series and the fourth PMOS transistor 9 pmos_9, the fifth PMOS transistor pmos10, and the sixth PMOS transistor pmos_11, which are connected in parallel, A second NMOS transistor nmos_7 connected in series with the first NMOS transistor nmos_6, a third NMOS transistor nmos_8 and a fifth NMOS transistor nmos_10, A MOS transistor nmos_9 and a sixth MOS transistor nmos_11 are connected in series.

※ Note: It is disclosed by the contents of the first application.