KR100701200B1 - Complementary logic circuit for constant power consumption - Google Patents

Abstract

The present invention provides a complementary logic circuit device and complementary logic for minimizing power consumption inconsistency and maintaining power consumption by symmetrically configuring two complementary relation circuits included in an NMOS logic circuit to be resistant to security attacks through power analysis. It relates to a circuit configuration method. To this end, the present invention is a complementary logic circuit device for making a constant power consumption, comprising a first logic circuit portion and a second logic circuit portion in a mutually complementary relationship, wherein the first logic circuit portion and the second logic circuit portion It is characterized by being configured symmetrically.

Description

Complementary logic circuit for constant power consumption

1 is a block diagram of a complementary logic circuit device according to the prior art.

2 is a block diagram of a complementary logic circuit device for making power consumption constant according to the present invention;

3A and 3B are truth table diagrams for the construction of a complementary logic circuit arrangement that makes power consumption constant in accordance with the present invention;

4 is a diagram of various embodiments of a logic gate circuit capable of constructing a complementary logic circuit arrangement that makes power consumption constant in accordance with the present invention.

5 is a flow chart of a method of constructing a complementary logic circuit that makes power consumption constant in accordance with the present invention.

<Description of the symbols for the main parts of the drawings>

10.Load and output circuit

100 ... Complementary logic circuit device

200 logic circuit

210 first logic circuit

260 ... second logic circuit

212, 214, 262, 264 ... parallel circuit

300 ... clock cutout circuit

Q1,2, ..., Q8 ... NMOS transistors (NMOS gate)

The present invention relates to a complementary logic circuit device and a method of configuring a complementary logic circuit for power consumption of the same type, and more specifically, to a circuit of two complementary relations included in an NMOS logic circuit to be resistant to a security attack through power analysis. The present invention relates to a complementary logic circuit device and a complementary logic circuit configuration method for minimizing power consumption mismatch and making power consumption constant by symmetrical configuration.

As is well known to those skilled in the art, conventional logic circuits with complementary outputs are constructed in the form as shown in FIG.

Referring to Fig. 1, a conventional logic circuit having complementary outputs is composed of a circuit portion 10 which is in charge of a load and an output, and an NMOS logic circuit portion 20 which determines a logic value. In the conventional complementary logic circuit 1, the NMOS logic circuit 20 for determining two complementary output values is composed of two circuits 22 and 24, as shown in FIG. 22 and 24 have a dual relationship with each other. That is, if one circuit is configured in parallel, the other circuit has a configuration in which it is connected in series. It will be apparent to those skilled in the art that the circuit 22 is a circuit connected in series and the circuit 24 is connected in parallel in the NMOS logic circuit 20 of FIG. 1.

Therefore, in the conventional complementary logic circuit 1 as shown in FIG. 1, the form of power consumption generated at the time of discharge depends on which circuit the discharge is made through, and in the case of the circuit 24 configured in parallel The number of discharge paths in which the transistor is open also affects the form of power consumption. Since the discharge path is determined by the input value of the gate, a logic gate having a conventional complementary output shows a different power consumption form according to the input value, which is vulnerable to a security attack.

Accordingly, the technical problem to be achieved by the present invention is to symmetrically configure the circuits of two complementary relations included in the NMOS logic circuits to be resistant to security attacks through power analysis, thereby minimizing power consumption inconsistencies and making power consumption constant. It is to provide a complementary logic circuit device.

Another technical problem to be achieved by the present invention is complementary to minimize power consumption inconsistency and make power consumption constant by symmetrically configuring two complementary circuits included in NMOS logic circuits to be resistant to security attacks through power analysis. It is to provide a logic circuit configuration method.

SUMMARY OF THE INVENTION In order to achieve the above technical problem, a complementary logic circuit device having a constant power consumption, comprising: a first logic circuit portion and a second logic circuit portion in complementary relation to each other, wherein the first logic circuit portion And the second logic circuit portion are provided symmetrically, so that a complementary logic circuit device for constant power consumption is provided.

In a preferred embodiment of the complementary logic circuit device of the present invention, each of the first logic circuit portion and the second logic circuit portion includes four NMOS transistors, and the four NMOS transistors are connected in parallel in the left and right directions, and up and down. It has a configuration connected in series in the direction.

In a preferred embodiment of the complementary logic circuit device of the present invention, the first logic circuit portion and the second logic circuit portion form four discharge paths, which are entirely on-on and on. It is in the form of on-off, off-on and off-off.

In a preferred embodiment of the complementary logic circuit device of the present invention, the first logic circuit portion and the second logic circuit portion may be formed of any one of an AND / NAND gate circuit form, an OR / NOR gate circuit form, and an XOR / XNOR gate circuit form. .

According to another aspect of the present invention, there is provided a method of constructing a complementary logic circuit for keeping power consumption constant, the method comprising: constructing a first logic circuit portion and a second logic circuit portion that are complementary to each other; And constructing the first logic circuit portion and the second logic circuit portion symmetrically.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a preferred embodiment of a complementary logic circuit device and a circuit configuration method for constant power consumption according to the present invention will be described in detail with reference to the accompanying drawings. In the following description of the present invention, when it is determined that detailed descriptions of related well-known technologies or configurations may unnecessarily obscure the subject matter of the present invention, the detailed description will be omitted. In addition, terms to be described below are terms defined in consideration of functions in the present invention, which may vary according to the intention or custom of a user or an operator. Therefore, the definition should be made based on the contents throughout the specification.

In the following description, when the member according to the prior art and the member according to the present invention are the same, the same reference numerals used in the prior art are used as they are, and detailed description thereof will be omitted.

2 is a configuration diagram of a complementary logic circuit device for making power consumption constant according to the present invention, and FIGS. 3A and 3B are truth table diagrams for a configuration of the complementary logic circuit device for making power consumption constant according to the present invention. 4 is a diagram illustrating various embodiments of a logic gate circuit capable of constructing a complementary logic circuit device for keeping power consumption constant according to the present invention, and FIG. 5 illustrates a complementary logic circuit for constant power consumption according to the present invention. A flow chart of how to do it.

Referring to FIG. 2, the complementary logic circuit device 100 for keeping power consumption constant according to the present invention includes a load and output circuit unit 10 that is in charge of a load and an output, and an NMOS logic circuit unit 200 that determines a logic value. And a clock cutoff circuit unit 300. The logic circuit unit 200 includes a first logic circuit unit 210 and a second logic circuit unit 260 in a complementary relationship with each other, and the first logic circuit unit 210 and the second logic circuit unit 260 are included. Are symmetrically configured as shown.

The first logic circuit 210 and the second logic circuit 260 include four NMOS transistors Q1,2,3,4 (Q5,6,7,8), respectively, as shown. The NMOS transistors form parallel circuits 212, 214, 262, and 264 in left and right directions, and these parallel circuits are connected in series. Here, the first logic circuit unit 210 and the second logic circuit unit 260 respectively form four discharge paths, and these four discharge paths are on-on and on-off as a whole. ), Off-on and off-off.

As shown in FIG. 4, the first logic circuit unit 210 and the second logic circuit unit 260 as described above have an AND / NAND gate circuit form (FIG. 4A), an OR / NOR gate circuit form (FIG. 4B), and XOR / XNOR gate circuit form (FIG. 4C) and 2-To-1 Mux. It may be in any one of the gate forms (FIG. 4D).

A method of configuring a complementary logic circuit device for making power consumption constant according to the present invention constituted as described above includes a first logic circuit 210 and a second logic having a complementary relationship with each other as shown in FIG. Constructing the circuit unit 260 (S10); And symmetrically configuring the first logic circuit unit 210 and the second logic circuit unit 260 (S20).

The operation of the complementary logic circuit device and the complementary logic circuit configuration method for keeping the power consumption constant according to the present invention configured as described above will be described with reference to FIGS. 2 to 5.

As described above, the complementary logic circuit device 100 having a constant power consumption according to the present invention symmetrically configures the NMOS first and second logic circuit units 210 and 260 in a complementary relationship, thereby inconsistent power consumption. Minimize. Complementary logic circuit arrangement constructed in accordance with the present invention has the form shown in Fig. 2, wherein the two output values derived through such a circuit are complementary to each other:

In the above equations, the values of X and Y are determined by the truth table of the logic gate to be designed, as shown in Figs. 3A and 3B. In the circuit device of FIG. 2, the clock blocking circuit unit 300 using the clock located below is additional and may be omitted in consideration of design aspects.

Complementary logic circuit device 100, which makes the power consumption constant according to the present invention shown in FIG. 2, become one in which both transistors are turned on according to four discharge paths regardless of input values. The other one is the top transistor on and the bottom transistor off. One of the other two sets off-on and the other off-off. As a result, four discharge paths are allocated in a one-to-one relationship with one of on-on, on-off, off-on, and off-off settings. Therefore, the power consumption generated through them becomes as follows.

Therefore, the complementary logic circuit device which makes the power consumption constant according to the present invention have the same discharge path regardless of the input value, so that the power consumption is always kept constant.

4a to 4d show the basic gates included in a complementary logic circuit arrangement for keeping power consumption constant according to the invention, the apparatus according to the invention being combined with any load and output circuitry configured in a symmetrical form. Can be configured and used.

As described above, the complementary logic circuit device and the complementary logic circuit configuration method for keeping the power consumption constant according to the present invention include symmetrical circuits of two complementary relations included in the NMOS logic circuit to be resistant to a security attack through power analysis. This configuration provides the advantage of minimizing power mismatch and keeping power consumption constant.

Although a preferred embodiment of the present invention has been described in detail above, those skilled in the art to which the present invention pertains may make various changes without departing from the spirit and scope of the invention as defined in the appended claims. It will be appreciated that modifications or variations may be made. Therefore, changes in the future embodiments of the present invention will not be able to escape the technology of the present invention.

Claims (9)

A complementary logic circuit device for making power consumption constant, A first logic circuit portion and a second logic circuit portion in complementary relation to each other, wherein the first logic circuit portion and the second logic circuit portion are symmetrically configured, Each of the first logic circuit portion and the second logic circuit portion includes four NMOS transistors, and the four NMOS transistors are connected in parallel in the left and right directions, and are configured in series in the vertical direction. Complementary logic circuit device to make power consumption constant. delete The method of claim 1, The first logic circuit portion and the second logic circuit portion form four discharge paths, and these four discharge paths are entirely on-on, on-off, off-on, and off. Complementary logic circuit device to make the power consumption constant, characterized in that the-off form so that the power consumption generated through them become equal. The method of claim 1, And the first logic circuit portion and the second logic circuit portion are in the form of an AND / NAND gate circuit. The method of claim 1, And the first logic circuit portion and the second logic circuit portion are in the form of an OR / NOR gate circuit. The method of claim 1, And the first logic circuit portion and the second logic circuit portion are in the form of an XOR / XNOR gate circuit. In the complementary logic circuit configuration method to make the power consumption constant, Constructing a first logic circuit portion and a second logic circuit portion in complementary relation to each other; And Symmetrically configuring the first logic circuit portion and the second logic circuit portion, Each of the first logic circuit portion and the second logic circuit portion includes four NMOS transistors, and the four NMOS transistors are connected in parallel in the left and right directions, and are connected in series in the vertical direction. Complementary logic circuit construction method to make power consumption constant. delete The method of claim 7, wherein The first logic circuit portion and the second logic circuit portion form four discharge paths, and these four discharge paths are entirely on-on, on-off, off-on, and off. Complementary logic circuit configuration method of the constant power consumption, characterized in that the power consumption generated through them to be in the form of -off.

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