JPS6047519A - Logical circuit - Google Patents

Abstract

PURPOSE:To allow a circuit to operate at a high speed by making the gm of one IGFET larger than that of the other IGFET. CONSTITUTION:The AND.NOR gate consisting of the AND gate 52 and NOR gate 54 of a circuit which latches a signal (g) with a signal (h) comprises and N channel MOSFET. In this case, IGFET.T61 functions as a depletion type load MOSFET and T62, T63, and T64 serve as enhancement type drivers. When an input signal (i) is at a low level, T64 is off and the AND.NOR gate functions as a two-input NAND gate which inputs the signals (g) and (h). In this case, the gm of T63 is made larger than that of T62.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an insulated gate field effect transistor (hereinafter referred to as I
It relates to logic circuits that perform switching operations using GFETs.

In a logic gate that includes at least two IGFETs connected in series, such as a two-man NAND gate, one input may be a signal with little change, such as a switching signal, and the other input may be a signal that requires speed. be.

An example of this is a binary counter. FIG. 1 is a circuit diagram for one bit of the binary counter. In FIG. 1, 11 and 12 are NAND gates, RES is a signal for resetting a binary counter, a is a count input signal, and 15 to 17 are transfer gates.

The signal RES normally has a logic value of "1" and becomes "θ" only when resetting, and is a signal that does not change much. The other signal a requires speed.

FIG. 2 is a detailed circuit diagram of the NAND gate 11 formed of an N-channel MO8 type IGFET. In FIG. 2, FETT, □, is a deregression type and acts as a load resistance. Hereinafter, it will be referred to as load MO8. FET T□ and T
, is an enhancement type driver. Capacity C
4□ and CI2 are the input gate capacitances of FET T22 and T0n, respectively, and the capacitance C0□ is the load MOS T2□
The load capacitance includes the source diffusion layer capacitance of FET T2□ and the drain diffusion layer capacitance of FET T2□, and the capacitance C02 is the load capacitance of FET T2□.
It is the sum of the source diffusion layer capacitance of T and the drain diffusion layer capacitance of FET T.

Now, the overall transfer conductance of the driver (hereinafter g,
gm, which is an appropriate ratio with g of load MO8, .
It is assumed that the design is set to a value of t. FETT2. The gfu of gl,,,,F E T T,,g,Il of gi2
3, conventionally 1gffi22=g, , 23-2
×g1. It was designed to be lt. Therefore, the shape of each FET becomes large, and therefore the capacitance C
I□+c12yCol and C02 also became large.

Since the signal RES changes little and speed is not required, it is manually input to the FETs T and 3, which are close to ground potential. In this case, normally when RES is a logical value "1", FET T2.
is ON, the capacitor C02 is discharged and falls to the ground potential, and even if the signal a changes, the change is caused by the load capacitance "ol".
does not participate in Therefore, capacitance/C02 and FET
There is no problem even if the input gate capacitance C52 of T is slightly increased.

However, the FET to which signal a, which requires speed, is input
Increasing the input gate capacitance C, I and the load capacitance Col of T2□ brings about a deterioration in speed.

An object of the present invention is to provide a logic circuit that can operate at high speed.

In the configuration of the present invention, a plurality of insulated gate field effect transistors are connected in series between at least one of a power supply potential or a ground potential and an output line.

In the logic circuit, the input signal of the first insulated gate field effect transistor connected closest to the power supply potential or the ground potential is determined before the input signal of at least one other of the insulated gate field effect transistors,
The first insulated gate field effect transistor has a transfer conductance larger than the other insulated gate field effect transistors.

Next, the present invention will be described in detail with reference to the drawings.

First, as a first example, we will take up the NAND gate in the binary counter of FIG. 1 used to explain the conventional example. Increase the gm (gln41) of F'ETT0 (FET close to ground potential) to which the signal RES is input, and increase the gm (gln41) of F'ETT0 (FET close to the ground potential) to which the signal RES is input, and increase the gm (gln41) of F'ETT0 (FET close to the output line) to which the signal a is input.
gm (gall□) is small. If g and n of the total driver are g, , t, then each g is as follows.

gII+""' gmt ' gm2m ) gmt Now, if the signal REI is set to a logic value of "'0" (hereinafter referred to as low level), the FET, , will be off, and the output will be a logic value of "1" (hereinafter referred to as high level). ) and the binary counter is reset. Signal aK is not involved. Next, when the signal RES is at high level, FET T and 3 are ON.
Therefore, the capacitor CI,2 is discharged to the ground potential. Normally, in this state, the output value changes as the signal a changes, so although the capacitance C02 and the input gate capacitance C0 are large by 5-10, they do not adversely affect the speed. FIT
Since g and n of T, are about half of the conventional values, the input gate capacitance Ci1 is also reduced by half, IK.

Since the load capacitance Cof also decreases as the drain diffusion layer capacitance of the FET Tzz becomes smaller, the speed increases.

Next, as a second example, the circuit shown in FIG. 3 will be taken up. FIG. 3 shows a circuit that switches the output of the inverter 31 or the inverter 32 according to the signal eK. 33.34
is a transfer gate. No particular speed is required for the signal eld. If this circuit is constructed of C-MOS, the detailed circuit diagram will be as shown in FIG. In Figure 4,
FETT, , T42IT4. and T411 are P-channel O8FETs, FETs, T, , T
, 4T4. and T411tlN channel MO8F'E
It is T. These FETs are all enhancement type. F E T T close to the power supply potential or ground potential to which the signals e and e are input, 1. T, 4. T4. and 148
Increase 0gm and set FET Tax close to the output line.
By reducing g of -Tax-T411 and T476-, the speed becomes faster as in the first embodiment.

In the above two embodiments, one of the two manual inputs was a signal with little change and no speed requirement, but in short, the signal that does not require speed changes in value before the signal that requires speed. The present invention is useful when this has been determined.

So 1. The invention c can be applied when one signal is determined before the other signal. An example thereof will be described below as a third embodiment.

FIG. 5 is a circuit diagram of the third embodiment. This circuit is a circuit that latches the signal gk times the signal. Since the signal g is a latch signal, the signal g is determined before the signal g. Part of the circuit in FIG. 5 %AND gate 52
FIG. 6 is a detailed circuit diagram in which an AND NOR gate consisting of an NOR gate 54 and a NOR gate 54 is constructed using an N-channel MO8FET. In Figure 6, FET T, □ are deregression type load MO8% FETs T, , T, and T.
a2 is an enhancement type driver. now.

The signal amount is low level, that is, this circuit has a logic value.
0" is latched. Therefore, FETs T and 4 to which signal 1 is input are turned off, and this AN
The D NOR gate can be thought of as a two-man NOR gate with a signal g and a signal ri.

As mentioned above, signal g is determined before the latch signal, so signal g has more speed, so
Input to FET T, which is close to ground potential, and FET T,
Increase g of , . In this case, since the first and second embodiments do not have enough speed, there is a limit to the gm of the FET T63, but the time difference between the signal g and the signal g and the drive ability of the signal g should be set appropriately. FET
T,,g.

is the total gr of FETT62 and 'ran, (gl, l
t) It is possible to make it sufficiently larger. So F
The g of ETT6□ can be made close to g, and the same effects as in the first and second embodiments can be obtained.

As explained above, in the above embodiment, the IGFETV
In the logic circuit configured as above, a first IGFET close to the power supply potential or extended ground potential and a second IGFET close to the output line are connected in series between at least one of the power supply potential or the ground potential and the output line. and the first I
GFET gfl.

By making gI,l larger than the second IGFET, a high-speed logic circuit is obtained. As described above, according to the present invention, a logic circuit capable of high-speed operation can be provided.

In the above-mentioned embodiment, for convenience, the explanation was limited to the series connection of two stages of FETs;
The same effect can be obtained by increasing gffi of the FET to which a signal other than the speed-required signal is input, and by decreasing g of the FET to which the speed-required signal is input. Also, N channel MO8
I explained only FET and C-MOS, but P channel MO
Needless to say, it can also be applied to 8FET.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a conventional logic circuit and a binary counter (19-bit) for explaining the first embodiment of the present invention, and FIG. 2 is a circuit diagram of an N-channel MO8FET.
A detailed circuit diagram of the NAND gate 11 in FIG.
3 is a circuit diagram for explaining the second embodiment of the present invention, FIG. 4 is a detailed circuit diagram when the circuit of FIG. 3 is formed with C-MOS, and FIG. 5 is a circuit diagram for explaining the second embodiment of the present invention. FIG. 6 is a circuit diagram for explaining the third embodiment, and FIG. 6 is a circuit diagram for explaining the AND in FIG.
ANDNOR consisting of NO gate and NOR gate 54
It is a detailed circuit diagram in which the gate is configured with an N-channel MO8FET. 10- (in Figure 1 Figure z Figure 3 Figure 4

Claims (1)

[Claims] A plurality of insulated gate field effect transistors are connected in series between at least one of a power supply potential or a ground potential and an output line, and the first insulated gate field effect transistor is connected closest to the power supply potential or the ground potential. In a logic circuit in which an input signal of an effect transistor is determined before an input signal of at least one other of said insulated gate field effect transistors, the transconductance of said first insulated gate field effect transistor is determined before said other said insulated gate field effect transistor. A logic circuit characterized by having a transconductance larger than that of a transistor.