JPS5843904B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device that can easily configure various CMO8 logic circuits.

Conventionally, a logic circuit consisting of a combination of CMO3FETs is designed by designing a pattern for each required logic circuit, and determining how to arrange each transistor, how to make contacts, etc.
The configuration of the output stage, etc., had to be considered each time, but this method is time-consuming, and when the degree of integration becomes small, uniform and mechanical processing is desired.

The present invention is an attempt to meet such demands, and even if the performance is slightly degraded, a large number of transistor pairs of a standard type are arranged in advance in a predetermined pattern, and the wiring is simply a straight line with no intersections. It is an attempt to make it possible to construct various desired logic circuits simply by providing wiring in the form of wires.

The manufacturing method of a semiconductor device of the present invention includes a plurality of pairs of P and N channel transistors, each of which has independent source and drain regions on a semiconductor substrate, and whose gate electrode connects each transistor on the P channel side and the N channel side. The CMOS logic circuit is characterized in that a CMOS logic circuit is constructed by connecting source and drain regions using a plurality of conductor patterns arranged in parallel with each other along the arrangement direction. This will be explained in detail.

Figures 1a, b and c show embodiments of the invention.

In these figures, A-G are input signals and are shown in Figure 1a.
As shown in , inputs A and B are added to the two-person AND circuit A1, the output of the AND circuit A is added to the two-person AND circuit R1 along with the input C, and the output of the OR circuit R1 is added to the inputs E and 2. The output of the AND circuit A2 is added to the NOR circuit R4 together with the output of the two-person AND circuit A3 to which inputs F and G are added, and the output of the NOR circuit R4 is input from the inverter. It is output through a buffer circuit BP.

Figure 1 shows the logic circuit of P-f channel FET array P.
It consists of 8 CMO circuits with N-channel FET rows N, and P-channel FETs P connected in parallel.
A and PB and N-channel FET N connected in series
A and NB form an AND circuit A1, and a P-channel FET connected in series with the parallel connection of PA and PB. An N-channel FET No. connected in parallel with the series connection of PC, NA and NB forms an OR circuit R1. .

Also, P-channel FETs PD, PE connected in series
N-channel FETs ND and NE connected in parallel constitute OR circuit R2, and N-channel FE connected in series with P-channel FET ppPG connected in parallel.
T NFNG constitutes an AND circuit A3. Furthermore, an AND circuit A2 consists of the parallel connection of PA-PC, PD, and PE, and the NA
- Consists of series connection of No, ND, and NE, NOR circuit R
4 is the series connection of PA-PE, PF, and PG and NA-N
It consists of parallel connection of E, NF, and NG.

That is, in the CMO8 circuit, the AND circuit is connected in parallel for the P channel and connected in series for the N channel, and the OR circuit is connected in series for the P channel and connected in parallel for the N channel.

The buffer circuit BF is composed of three parallel P-channel FETPs.
1 to P3 and N-channel FETs Nl-N3 are connected in series.

FIG. 1C shows a specific example in which the logic circuit shown in FIG. 1a or b is constructed using the semiconductor device of the present invention.

As shown in this figure, first, in the present invention, a large number of FET elements each consisting of a source region S1, a drain region D1, and a gate electrode G are separated on a semiconductor substrate SUB into P-channel type devices in the upper stage and N-channel type devices in the lower stage. A large number of them are arranged in a straight line.

The source region S and drain region of each adjacent FET are made independent from each other, and the gate electrode G connects the P-channel FET and the N-channel FET to each other.

Such a board may be prepared in advance as a semi-finished product, or may be manufactured as needed, but in any case, using such a board allows a CMO8 logic circuit to be easily constructed.

That is, to configure the logic circuit shown in FIG. 1a and b, P, N
On each channel-type FET, there are three continuous or discontinuous parallel wiring lines L1. extending along the FET pair arrangement direction Q. L2. L3 and L4. L5. L6 may be applied, and contact may be made by opening the window W as shown by the mesh lines.

With this wiring, for example, the drain of transistor PA is set to V
The DD line L line section 1 source is the source of transistor PB,
The drain of PB is connected to VDD line L line section 1, the drain of transistor NA is connected to intermediate output line L4, the source is connected to the drain of transistor NB, and AND circuit A1
is configured.

The same applies to other AND and OR circuits.

The same holds true for the inverter section, which serves as a buffer and includes transistors P1 to N3.

In this semiconductor device, each P channel and N channel FE
All logic circuits that can be formed within the range of not exceeding three stages on the T side can be easily configured by changing only the wiring.

Although it is possible to configure a logic circuit with four or more stages by using four or more wires instead of three wires each, if the number of stages increases too much, the operation delay becomes noticeable, which poses a practical problem.

There are 82 types of 3-level stacked logic circuits, and 343 types of 4-level stacked logic circuits.
There are 0 types.

Therefore, the semiconductor device of the present invention can be used to fabricate a considerably large number of logic circuits.

A method for determining the number of stages from a logic diagram is to focus on OR circuits on the P channel side, and on AND circuits on the N channel side, and if these are present, it is assumed to be two stages.

In the circuit of Figure 1a, the AND circuit A1 on the P channel side is one stage, and can be considered in the same way as the input C etc.
The next OR circuit R1 has two stages, which is the same as the two stages of OR circuit R2.

Next AND circuit A2. A3 also does not need to be counted in terms of the number of stages, but the next NOR circuit R4 (in terms of the number of stages (this is the same as OR)
is 2 stages, or 1 stage plus, making the total 3 stages.

On the N channel side, the AND circuit and OR circuit are interchanged, and the first stage AND circuit A1 is replaced by two stages, and the next stage AND circuit A2
is plus one stage, totaling 3 stages, and the AND circuit A3 which is connected in parallel to NOR circuit R4 has 2 stages, so take the larger one and get 3 stages.
Since the OR circuit R1, rt2°R4 has 0 stages, this circuit has N stages (the Jannel side also has 3 stages).

According to the present semiconductor device, the three-level stacked logic circuit has P.

N L1 to L3 on each channel side. Necessary connections can be made using the three conductive wires L4 to L6 without crossing each other.

However, the order of the input signals A, B, C, . . . is not arbitrary, but is fixed to a predetermined order as shown in the figure.

Therefore, pin scrambling is required to change the order of input signals between the input terminal and the device.

FIG. 2 shows an example of this pin scrambling.

In this figure, IN is the input consisting of A-F, and LS is the first
In the CMO8 complex logic cell shown in the figure, PS is a pin scrambling section and OUT is an output terminal.

By using a large number of logic cells as shown in Figure 1, it is possible to create a multi-input, multi-output logic gate array, but in this case, the order of inputs to the logic cells may differ depending on the type of logic. This can be accomplished by rearranging the input order using the pin scrambling section PS.

This pin scrambling section PS extends the gates of each cell LS and connects predetermined gates by crossing lines La, Lb, . It becomes possible to add G.

In addition, the number of 71 element pairs used in this semiconductor device is determined according to the number of manpower, and in the case of A-F7 manpower as in this example, 7 pairs are used.

As is well known, the output of the CMO8 logic circuit is either VSS or VDD.
It is a ratioless type, so even if the transistors are connected in series in one row without changing the transistor size, the output level will not be affected.

This is very effective in terms of pattern layout, and the size of each transistor is made constant in the semiconductor device of the present invention as well.

However, in this case, as the number of series-connected stages increases, the impedance of the circuit increases and the delay time increases.

Therefore, in the present invention, a buffer BF is inserted (the fan-out is 1) to standardize the circuit characteristics for each stage.

The reason why three FETs are connected in parallel in the buffer stage is due to the capacity, and the number is not limited to this.

Kowa is effective for LSI design using CAD (Computer Appointed Design).

As explained in detail above, according to the present invention, it is possible to mechanically layout a CMO8 logic circuit,
Design and production become extremely easy.

[Brief explanation of the drawing]

FIGS. 1a, b, and c are logic diagrams and wiring diagrams showing a first embodiment of the present invention, and FIG. 2 is a wiring diagram showing an example of pin scrambling. In the drawing, SUB is a semiconductor substrate, S is a source region, D is a drain region, G is a gate electrode, L1 to L6 are conductor patterns, and BF is an inverter forming a buffer.

Claims (1)

[Scope of Claims] 1. A semiconductor substrate, each having an independent source region and a drain region, and a gate electrode connected to each transistor on the P-channel side and the N-channel side;
A method for manufacturing a semiconductor device comprising arranging a plurality of pairs of N-channel transistors and connecting source and drain regions using a plurality of conductor patterns extending in parallel along the arrangement direction to form a CMO8 logic circuit. . 2 Part of P, N channel transistor pair, CM
2. The method of manufacturing a semiconductor device according to claim 1, further comprising configuring an inverter that standardizes circuit characteristics of an O8 logic circuit.