JP3289736B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a new custom LSI which can realize various logic functions with almost the same circuit pattern.

[0002]

BACKGROUND OF THE INVENTION The degree of integration of semiconductor integrated circuits is improving year by year with the progress of miniaturization of transistors. With the improvement in the degree of integration, the function of a logic LSI that can be realized on one chip has been dramatically increased.

As a result, 32-bit and 64-bit microprocessors have been developed, and are mounted on various industrial and consumer devices to perform very sophisticated control. However, a method of performing a predetermined control by programming a general-purpose chip such as a microprocessor according to each purpose has a disadvantage that the processing speed is generally slow.

Therefore, it is important to develop a dedicated LSI chip suitable for each application purpose and to incorporate what is called a custom LSI chip into each system. However, the development of a dedicated chip requires a great deal of time and cost, and is rapidly progressing. At present, it is not fully responding to the needs of the world.

Further, in a semiconductor factory that produces chips, a large number of L
It is necessary to store an original SI pattern (called a reticle) and set it on a stepper (pattern projection transfer device) as needed to produce an LSI. In particular, it takes time to replace this reticle. There have been problems such as a significant decrease in production efficiency.

[0006] Therefore, development of a technology capable of producing various custom LSIs using the same reticle as much as possible has been desired.

There is a gate array that meets such needs. Gate array is NMOS and PMO
It is configured by arranging a large number of identical circuit blocks each having two S transistors as a set on each chip. Then, the necessary logic functions are realized by appropriately connecting the transistors with a conductive wiring pattern such as Al. AND, NAN
Simple circuits such as D, OR, and NOR can be configured relatively easily, but if a slightly advanced function is to be realized, a large number of transistors are required, and the formation of a very complicated wiring pattern is required. For example, a simple three-input
Just realizing Exclusive NOR requires as many as 38 transistors.

[0008] For the above reasons, in order to cope with various logic circuit configurations, they lack flexibility and are inferior to custom LSIs in terms of integration of functions.

However, for applications that require only a small number of chips for special applications, there is nothing other than a gate array that can cope with them, so they are still partially used.

[0010] However, it takes time to design to realize the necessary logic functions, and further technical improvements are expected. PLA can be easily designed.
(Programmable Logic Array) can be realized on a chip by cutting a fuse etc. as it is on a function expression expressed by Boolean algebra, but this can be realized by
Limited to small ones. There are also many problems in terms of high-speed operation and reliability assurance of the circuit.

[0011]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor integrated circuit which can easily provide a very sophisticated custom LSI. And

[0012]

A semiconductor integrated circuit according to the present invention comprises a plurality of circuit blocks having a plurality of input terminals and at least one output terminal and having the same circuit configuration. In a semiconductor integrated circuit including at least a part of a configured logic circuit, the circuit block may be an MO.
In addition to having at least two stages of inverters constituted by S-type semiconductor devices, each block is provided with at least one layer of wiring patterns having different patterns as necessary, and the output of each block is provided by the wiring pattern. The function form is defined so that the signal becomes a predetermined function of the input signal.

[0013]

According to the present invention, all logic circuits can be configured with a common mask except for the metal wiring mask, and the performance of the custom LSI can be greatly improved.

[0014]

Embodiments will be described below with reference to the drawings.

FIG. 1A is a circuit diagram showing a first embodiment of the present invention.

As an example, six circuit blocks 101a to 101f having the same circuit configuration are shown, and a wiring 102 between the blocks is also drawn. The wiring 102 is formed of, for example, an aluminum wiring pattern which is the last pattern in an LSI manufacturing process. Y ₁ , Y ₂ , Y
₃ is an output terminal of this logic circuit. Each block has the same structure except for the wiring pattern (a wiring pattern of aluminum in this example), and the structure of the block is shown in FIG. 1B, for example. In the figure, reference numeral 103 denotes an N-channel neuron MOS transistor (νMOS) 103a and a P-channel νMOS (103).
b) and is referred to as a main inverter. The input gates 103-1 and 103-
2, 103-3, 103-4, 103-5 and floating gate 103-6 have a coupling capacitance of C
_{1: C 2: C 3:} C 4: C 5 = 2: 1: 2: 1: and 1 lead. Numerals 104, 105, and 106 denote similar νMOS inverters, and are called inverters A, B, and C, respectively.

In the inverter A, the input gates 104-1,
104-2, 104-3, 104-4, 104-5, 1
The coupling capacitance between the transistor 04-6 and the floating gate 104-7 is respectively C ₁ : C ₂ : C ₃ : C ₄ : C ₅ : C ₆ : =
2: 1: 1: 1: 1: 1, and the same applies to the inverters B and C. Inverter A,
B and C which provide signals to the main inverter 103 are called pre-inverters.

Reference numeral 107 denotes a normal CMOS inverter, which outputs an output signal Y by inverting the output Y 'of the main inverter 103.

This circuit block has two inputs X ₁ and X ₂
In contrast, a circuit that outputs one signal Y is provided. Y
Y = f (X ₁ , X ₂ ) (1) As a result, a result obtained by performing a specific Boolean function operation on the 2-bit binary inputs X ₁ and X ₂ is output. The form of the Boolean function is based on the input signals A _{1 to} A ₄ , B ₁ to
It can be specified by connecting each terminal of B ₄ and C _{1 to} C ₄ to V _DD or V _SS . That is, the function form is determined only by the aluminum wiring pattern that determines the connection status of these input terminals. In fact, in the circuit of FIG.
All 16 types of Boolean functions for the two-input signals X ₁ and X ₂ can be realized.

In order to explain the operation of the circuit shown in FIG. 1B, first, the structure and operation principle of the νMOS will be described. FIG. 2A shows an example of a cross-sectional structure of a 4-input N-channel νMOS transistor (N-νMOS).
203 is a source and a drain formed of an N ⁺ diffusion layer,
204 denotes a gate insulating film provided on the channel region 205 between the source and drain (e.g. SiO ₂ film) 206 is electrically insulated from the floating gate electrode in a state of potential floating, 207, for example of SiO ₂ or the like The insulating films 208a, 208b, 208c and 208d are input gates and electrodes. FIG. 2B is a diagram further simplified for analyzing the νMOS operation. Assuming that the capacitance coupling coefficient between each input gate electrode and the floating gate is C ₁ , C ₂ , C ₃ , C ₄ as shown in the figure, and the capacitance coupling coefficient between the floating gate and the silicon substrate is C ₀ , the potential φ of the floating gate _F is given by the following equation. φ _F = (1 / C _TOT ) (C ₁ V ₁ + C ₂ V ₂ + C ₃ V ₃ + C ₄ V ₄ ) where C _TOT ≡C ₀ + C ₁ + C ₂ + C ₃ + C ₄ V ₁ , V ₂ , V ₃ , V ₄ are input gates 208 respectively.
a, 208b, 208c, 208d, and the potential of the silicon substrate is assumed to be 0 V, that is, grounded.

Now, the potential of the source 202 is set to 0V. That is, a value measured with the potentials of all the electrodes as a source reference is used. Then, the νMOS shown in FIG. 2 is the same as a normal N-channel MOS transistor if floating gate 206 is regarded as a normal gate electrode, and its gate potential φ _F becomes larger than threshold value (V _TH ^* ). Source 2
An electron channel (N-channel) is formed in a region 205 between the second and the drain 203, and the source and the drain are electrically connected. That is, when the condition of (1 / C _TOT ) (C ₁ V ₁ + C ₂ V ₂ + C ₃ V ₃ + C ₄ V ₄ )> V _TH * is satisfied, the νMOS conducts (ON).

The above is the description of the N-channel νMOS transistor. In FIG.
2. There is also a device in which the drain 203 and the substrate 201 are all of the opposite conductivity type. That is, the substrate is N-type,
The source / drain is a νMOS formed of a P ⁺ diffusion layer, which is a P-channel MOS transistor (P-νM
OS).

In FIG. 1A, for example, block 1
In the case of 01d, the input of the pre-inverter is wired in the block as shown in FIG.

[0024]

(Equation 1) That is, the exclusive OR of X ₁ and X ₂ is negated (EXCLU).
SIVE NOR).

Next, the operation of the circuit shown in FIG. 1C will be described. Now, when the potential φ _F of the floating gate 104-7 of the pre-inverter A is calculated, φ _F = (C ₁ X ₂ + C ₂ X ₁ + C ₃ A ₁ + C ₄ A ₂ + C ₅ A ₃ + C ₆ A ₄ ) / C _TOT = (V _DD / 7) (2X ₂ + X ₁ + A ₁ + A ₂ + A ₃ + A ₄ ) (3) However, for simplicity, C ₀ was ignored because C _{0 <<} C _TOT .

Since A ₁ = A ₂ = A ₃ = V _DD and V ₄ = 0,
Equation (3) is When plotting φ _F with respect to the combination of (X ₁ , X ₂ ), it becomes like a straight line 108 in FIG. 1D. In the figure, a threshold line 109 is a line indicating the inversion voltage of the inverter, and (1/2) V _DD is applied to all the inverters.
Is set to That is, the inverter A has (X ₁ ,
X ₂ ) = (0,0) is not inverted and V _DD is output, but is inverted for inputs (0,1), (1,0) and (1,1). And the output becomes 0. This output is input to the input gate 103-3 of the main inverter.

Similar considerations are made for the inverters B and C, and the floating gate 103 of the main inverter is
FIG. 1E shows the potential φ _F of −6 for the combination of (X ₁ , X ₂ ), and FIG.
The effects of the outputs of B and C are clearly shown. According to this figure, the main inverter is inverted at (X ₁ , X ₂ ) = (0,
0) and (1, 1), and then Y ′ =
0, Y = 1. That is, the circuit is XNOR.

Similarly, the circuit of FIG. 1B can realize any Boolean function by connecting A _{1 to} A _{4 and the} like to V _DD or V _SS . For example, AND, O
R, NAND, NOR, EXCLUSIVE NOR,
Table 1 shows connection methods for realizing circuits such as EXCLUSIVE OR and INHIBIT.

INHIBIT is a function called an inhibit gate. When X ₂ = 0, the output is always 0, and X ₂ =
To 1, then X ₁ is a circuit which acts as an inverter.
Shown changes in phi _F of the main inverter for realizing this circuit is shown in FIG 1 (f).

FIG. 1 (g) shows an example in which predetermined connections are made for each block in FIG. 1 (a) by using logical symbols. Obviously, any logical function can be expressed simply by changing the connections in each block.

According to the present invention, all the LSIs are prototyped using the same mask (reticle) until Al wiring is performed, and only the Al pattern corresponding to a specific function may be used. A logic circuit can be manufactured similarly to the gate array. However, instead of combining single transistors as in a gate array, FIG.
Since the basic circuit of (b) is used, all the Boolean functions for the two inputs X ₁ and X ₂ can be realized with the same constituent blocks, and the circuit design becomes extremely simple. Also, the wiring for designating the function for each block is shown in FIG.
For example, as shown in FIG.
Assuming that 4-4, 104-5, 104-6 are made of polysilicon, it is only necessary to determine how many of the respective contacts are connected to V _DD and V _SS. realizable. Of course, it goes without saying that two or more layers of metal wiring may be used. in this case,
In particular, the degree of freedom of the wiring 102 between the blocks increases, and the configuration of the logic circuit becomes easier.

Although the normal inverter 107 is provided in the circuit shown in FIG. 1B, this is not always necessary and may be omitted. Alternatively, one or more stages may be added. In this way, a large fan-out can be obtained if necessary. Alternatively, as shown in FIG. 1 (h), several stages of inverters 107 ′, 107 ″ and the like may be added so as to extract the respective outputs. At this time, if the output transistors 107 'and 107''are made large, a large fan-out can be obtained.
The output line can be selected as needed. In addition, the forward output or the inverted output can be arbitrarily selected, and the degree of freedom in logic design is further increased.

It goes without saying that the output stage may be provided with, for example, a flip-flop as shown in FIG.

Regarding the inverters A, B, C, etc., the signals may be input to the main inverter via one or more ordinary inverters.

[0035] In addition, the floating gate need not be always floating, as appropriate V _DD via a switch
Alternatively, it may be connected to V _SS or another potential.

It goes without saying that the whole circuit may be operated in synchronization with the clock.

The four input gates A _{1 to} A ₄ are replaced with _two input gates A ₁ ′ and A ₂ ′, and the respective coupling capacitances C ₃ ′ and C ₄ ′ are represented by C ₃ ′: C ₄ '= 1: 2 may be selected. However, at this time, C ₃ ′ + C ₄ ′ = C
₃ + C ₄ + C ₅ + C ₆ . A similar result can be obtained by connecting the two contact holes to _VSS or _VDD .

FIG. 3A shows a second embodiment of the present invention.

The difference from the first embodiment is that the input of the basic block is a 3-bit input of X ₁ , X ₂ and X ₃ . For example, input X ₁ ,
The coupling capacitances between X ₂ , X ₃ , A ₁ , A ₂ , A ₃ , A ₄ and the floating gate are represented by C ₁ , C ₂ , C ₃ , C ₄ , C ₅ , C ₆ ,
When C ₇ has a _{C 1 = C 2 = C 3} = C 4 = C 5 = C 6 = C 7.

The same applies to the other pre-inverters B and C. As for the main inverter, the input gate capacitance is 1: 1: 1: 2: 1: 1 from the top.

[0041] Now, A ₁ ~ As shown in FIG. 3 (a)
And _{A 4, B 1 ~B 4,} C 1 ~C 4 are connected. FIG. 3 shows the relationship between φ _{F of the} pre-inverter A and X ₁ , X ₂ , and X ₃ .
It is shown in (b).

Since the coupling capacitances of X ₁ , X ₂ , and X ₃ are all the same, the value of φ _F is determined only by the number of inputs of one of the three. That is, the pre-inverter A
Is inverted when the number of 1s becomes 2 or more, and the output becomes 0. In the same consideration, the output of the pre-inverter B is always 1 (V _DD ), and the output of the pre-inverter C is always 0. Therefore, the φ _F of the main inverter is as shown in FIG. 3C, and the inverter is inverted only when the number of 1s in the input is one or three, and Y ′ = 0, that is, Y = 0. . That is, Y = X ₁ + X ₂ + X _3, that is, Y is an exclusive logical sum (EXCLUSIVEOR) of three inputs X ₁ , X ₂ , and X ₃ .

In the conventional circuit, 40 transistors were required, but this is realized by 10 transistors. That is, an extremely complicated circuit realized by a conventional gate array is realized very easily. This is a great advantage of the present invention.

The circuit shown in FIG. 3A operates on three input signals.
This is a circuit that can express all symmetric functions 16.

Also, as shown in FIG.
For the three inputs X ₁ ′, X ₂ ′, and X ₃ ′, whether or not the input signal is input through an inverter can also be selected using an aluminum pattern. And 12 including some asymmetric functions
The circuit can express eight functions, and the degree of freedom is further increased.

When the same circuit X ₁ ′ is input to X ₁ and X ₂ as shown in FIG. 3E, for example, as shown in FIG. All Boolean functions for the two inputs X ₁ ′ and X ₂ ′ can be realized.

That is, if the block shown in FIG. 3A is used, it becomes a very flexible block which can support all symmetric functions of three inputs and all functions of two inputs.

The above embodiment is for the case of three inputs.
It goes without saying that a block with more inputs may be prepared.

For example, a circuit capable of expressing all 512 8-input symmetric functions can be constituted by a similar circuit having nine stages of pre-inverters and one stage of main inverter. This circuit is shown in FIG.
As in the case of (d), if the input stage is made to be able to select whether or not the input is inverted, 131,07 in the same block that does not exist.
Two functions can be expressed.

Also, as in FIG. 3E, if two inputs and four inputs are bundled and each of them is made one input, it can be used as a circuit capable of expressing all functions of three inputs.

According to the present invention, a custom LSI can be configured very easily, and the configuration of a logic circuit can be greatly improved.

In this embodiment, only the configuration of the random logic circuit has been described. However, it is needless to say that a part of the circuit may be formed with a wiring which feeds back an output to an input stage and has a memory function. No.

Further, a RAM pattern may be provided on the same chip to add a memory function, or a general-purpose microprocessor may be integrated on the same chip.

With some blocks left unwired,
After the function test, a block that does not work due to a defect or the like may be replaced as a spare. This is the RED in the logic circuit
This is a concept of chip rescue by UNDANCY, which has been realized only with a memory until now. REDU
This is an epoch-making invention in which NDANCY rescue is realized by a logic circuit.

Further, the circuit blocks shown in FIGS. 1B and 3A do not need to be all formed in exactly the same pattern. It goes without saying that the basic circuit configuration should be common. If necessary, a block composed of large-sized transistors may be arranged in the output stage.

[0056]

[Table 1]

[0057]

According to the present invention, all the logic circuits can be configured with a common mask except for the metal wiring mask, and the performance of the custom LSI can be remarkably improved.

[Brief description of the drawings]

FIG. 1A is a circuit diagram showing a first embodiment of the present invention. FIG. 1B is a diagram showing the structure of a block. FIG. 1C is a diagram showing the input of the pre-inverter. FIGS. 1C and 1D are diagrams in which φ _F is plotted with respect to the combination of (X ₁ , X ₂ ). FIG. 1E is a diagram showing the potential φ _F of the floating gate 103-6 of the main inverter for the combination of (X ₁ , X ₂ ). And 1 (f) show the subimages is a view showing a change in phi _F of the main inverter. FIG. 1G is a diagram showing an example in which predetermined connections are made for each block in FIG. FIG. 1H and FIG. 1I are diagrams showing modified examples relating to output.

FIG. 2A is a diagram illustrating an example of a cross-sectional structure of a 4-input N-channel νMOS transistor (N-νMOS). FIG. 2B is a further simplified diagram of FIG. 2A for analyzing the νMOS operation.

FIG. 3A is a diagram showing a second embodiment of the present invention. FIG. 3B shows φ _F and X ₁ of the pre-inverter A,
It is a graph showing the relationships of X _2, X _3. Figure 3 (c) is a view showing a change in phi _F of the main inverter. FIG. 3 (d)
FIG. 3E is a diagram showing an input example of a circuit.

[Explanation of symbols]

101a to 101f circuit block, 102 wiring between blocks, 103a N-channel neuron MOS transistor (νMOS), 103b P-channel νMOS, 103 CMOS inverter, 103-1, 103-2, 103-3, 103-4, 1
The coupling capacitance between the 03-5 input gate and the 103-6 floating gate is C ₁ : C ₂ : C ₃ : C ₄ : C ₅ = 2:
1: 2: 1: 1. 104, 105, 106 νMOS inverters, 104-1, 104-2, 104-3, 104-4, 1
04-5, 104-6 input gate, 104-7 floating gate, 107 CMOS inverter, 201 P type silicon substrate, 202, 203 source and drain formed by N ⁺ diffusion layer, 204 gate insulating film (for example, SiO
₂ film), a channel region between 205 source and drain, 206 electrically insulated potentially floating state, 207 SiO ₂ or the like of the insulating film,

Continuation of the front page (51) Int.Cl. ⁷ Identification code FI H01L 27/118 H01L 29/78 371 29/788 29/792 H03K 19/173 101 (73) Patentee 598158521 I & F Corporation Tokyo Cosmos Hongo Building, 1-4 1-4 Hongo, Bunkyo-ku, Tokyo (72) Inventor Naoshi Shibata 5-2 Nihondaira, Taihaku-ku, Sendai, Miyagi (72) Inventor Tadahiro Omi Yonegabukuro, Aoba-ku, Sendai, Miyagi JP-A-3-6679 (JP, A) JP-A-2-113494 (JP, A) JP-A-2-281759 (JP, A) JP-A-2- 224190 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/10 H01L 21/822 H01L 21/8247 H01L 27/04 H01L 27/115 H01L 27/118 H01L 29/788 H03K 19/173

Claims (5)

(57) [Claims] 1. A semiconductor having a plurality of input terminals and at least one output terminal, and at least partially including a logic circuit configured by arranging a plurality of circuit blocks having the same circuit configuration. In the integrated circuit, the circuit block has at least two stages of inverters configured by MOS type semiconductor devices, and each block is provided with at least one wiring pattern having a different pattern as needed. A semiconductor integrated circuit, wherein a function form of the block is defined so that an output signal of each block becomes a predetermined function of an input signal by the wiring pattern. 2. A semiconductor device having a semiconductor region of one conductivity type on a substrate,
A source and drain region of opposite conductivity type provided in this region, and a floating gate electrode in a potential floating state provided via a first insulating film in a region separating the source and drain region. Having a plurality of control gate electrodes capacitively coupled to the floating gate electrode via a second insulating film
2. The semiconductor integrated circuit according to claim 1, wherein an OS transistor is used as said MOS semiconductor device. 3. The circuit block is configured such that the input signal is a binary signal of 1 or 0, and the function form can be represented by any of all possible Boolean functions for the input signal. The semiconductor integrated circuit according to claim 1, wherein: 4. The circuit block is configured such that the input signal is a binary signal of 1 or 0, and the function form can be represented by any of all possible Boolean functions symmetric with respect to the input signal. The semiconductor integrated circuit according to claim 1, wherein: 5. The apparatus according to claim 4, wherein the same signal is input to 2 ⁿ (n is 0 or a positive integer) input terminals of the plurality of input terminals. Semiconductor integrated circuit.