JPS6476211A - Digital logic integrated circuit - Google Patents
Digital logic integrated circuitInfo
- Publication number
- JPS6476211A JPS6476211A JP62232587A JP23258787A JPS6476211A JP S6476211 A JPS6476211 A JP S6476211A JP 62232587 A JP62232587 A JP 62232587A JP 23258787 A JP23258787 A JP 23258787A JP S6476211 A JPS6476211 A JP S6476211A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- data processing
- executed
- input
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
PURPOSE:To execute a processing at a high speed not through a level converting circuit concerning a specified data processing by providing an auxiliary logic circuit between the level converting circuit and an input and output terminal and connecting it so that the data can be mutually transferred. CONSTITUTION:When the normal data processing is executed by using an internal circuit 1, a signal inputted from input and output terminals 51-5n is sent through input and output circuits 21-2n in interface parts 41-4n and level converting circuits 31-3n to the circuit 1 and the prescribed data processing is executed. When the specified easy data processing of AND operation or OR operation, etc., which are determined in advance, is executed with using auxiliary logic circuits 61-6n, the data which are inputted from the input terminal in the terminals 51-5n, are inputted through the circuits 21-2n in the correspondent interface parts 41-4n to the circuits 61-6n. The prescribed processing is executed and the obtained data are directly outputted to the output terminal in the terminals 51-5n. Thus, since the specified data processing, which is processed by the circuits 61-6n, is not needed to pass through the circuits 31-3n, the data processing can be executed at the high speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62232587A JPS6476211A (en) | 1987-09-18 | 1987-09-18 | Digital logic integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62232587A JPS6476211A (en) | 1987-09-18 | 1987-09-18 | Digital logic integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6476211A true JPS6476211A (en) | 1989-03-22 |
Family
ID=16941696
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62232587A Pending JPS6476211A (en) | 1987-09-18 | 1987-09-18 | Digital logic integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6476211A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05218203A (en) * | 1991-11-20 | 1993-08-27 | Nec Corp | Semiconductor integrated circuit device |
JP2021001779A (en) * | 2019-06-20 | 2021-01-07 | 富士通株式会社 | Semiconductor integrated circuit and testing method of semiconductor integrated circuit |
-
1987
- 1987-09-18 JP JP62232587A patent/JPS6476211A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05218203A (en) * | 1991-11-20 | 1993-08-27 | Nec Corp | Semiconductor integrated circuit device |
JP2021001779A (en) * | 2019-06-20 | 2021-01-07 | 富士通株式会社 | Semiconductor integrated circuit and testing method of semiconductor integrated circuit |
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