JPS55156425A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS55156425A
JPS55156425A JP6390279A JP6390279A JPS55156425A JP S55156425 A JPS55156425 A JP S55156425A JP 6390279 A JP6390279 A JP 6390279A JP 6390279 A JP6390279 A JP 6390279A JP S55156425 A JPS55156425 A JP S55156425A
Authority
JP
Japan
Prior art keywords
signal
output
pin
terminal
functions
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6390279A
Other languages
Japanese (ja)
Inventor
Shuichi Torii
Shigeo Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP6390279A priority Critical patent/JPS55156425A/en
Publication of JPS55156425A publication Critical patent/JPS55156425A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1731—Optimisation thereof
    • H03K19/1732—Optimisation thereof by limitation or reduction of the pin/gate ratio

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce input-output pins in number by allowing an external pin to function as an input control terminal and output signal terminal. CONSTITUTION:When external pin P has high impedance, signal (a) is passed through inverting circuits IN1 and IN2 to obtain output signal (a') at pin P. At this time, although exclusive-OR circuit EX generates output (b) of ''1'' as long as delay time depending upon IN1 and IN2, flip-flop FF operates with clock signal phi which never overlaps with both edges of signal (a), so that its output will not change. In this case, pin P functions as an output signal terminal. On the other hand, when signal (a) becomes ''1'', signal (a') is ''1'', so signal (b) changes into ''1'' with pin P set to ''0'' forcibly. Then, FF fetches signal (b) by ''1'' of signal phi and output Q changes into ''1''. In this case, pin P functions as an input control terminal.
JP6390279A 1979-05-25 1979-05-25 Semiconductor integrated circuit Pending JPS55156425A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6390279A JPS55156425A (en) 1979-05-25 1979-05-25 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6390279A JPS55156425A (en) 1979-05-25 1979-05-25 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS55156425A true JPS55156425A (en) 1980-12-05

Family

ID=13242704

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6390279A Pending JPS55156425A (en) 1979-05-25 1979-05-25 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS55156425A (en)

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