JPS6424516A - Crc check circuit - Google Patents

Crc check circuit

Info

Publication number
JPS6424516A
JPS6424516A JP18025887A JP18025887A JPS6424516A JP S6424516 A JPS6424516 A JP S6424516A JP 18025887 A JP18025887 A JP 18025887A JP 18025887 A JP18025887 A JP 18025887A JP S6424516 A JPS6424516 A JP S6424516A
Authority
JP
Japan
Prior art keywords
flip
output
flops
input
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18025887A
Other languages
Japanese (ja)
Inventor
Riyouichi Danki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18025887A priority Critical patent/JPS6424516A/en
Publication of JPS6424516A publication Critical patent/JPS6424516A/en
Pending legal-status Critical Current

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  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To generalize a flip-flop in use and to reduce the scale of hardware by using only a data input and a clock input as inputs of the flip-flop and setting an initial state without resetting respective flip-flops. CONSTITUTION:Flip-flops(FFs) 11-1n whose number is equal to the largest degree (r) of a generating polynomial are cascaded in order through exclusive OR(EX-OR) circuits 20-2r-1, a gate circuit 4 is provided, and its output is input ted to the EX-OR circuits of the respective stages as a substitute for the output of the FF 1r of the final state. Namely, the gate circuit 4 inputs the output of the FF 1r of the final stage and a control signal to generate its output. This control signal has bit width equal to the largest degree of the generating polynomial and its output start point of time is coincident with the input start point of time of an operand signal. Consequently, the clear function of the flip-flops is not necessary and fast CRC check operation is enabled.
JP18025887A 1987-07-20 1987-07-20 Crc check circuit Pending JPS6424516A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18025887A JPS6424516A (en) 1987-07-20 1987-07-20 Crc check circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18025887A JPS6424516A (en) 1987-07-20 1987-07-20 Crc check circuit

Publications (1)

Publication Number Publication Date
JPS6424516A true JPS6424516A (en) 1989-01-26

Family

ID=16080111

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18025887A Pending JPS6424516A (en) 1987-07-20 1987-07-20 Crc check circuit

Country Status (1)

Country Link
JP (1) JPS6424516A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01115336U (en) * 1988-01-29 1989-08-03
JP2005160074A (en) * 2003-11-24 2005-06-16 Agilent Technol Inc Two input differential round accumulator

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01115336U (en) * 1988-01-29 1989-08-03
JP2005160074A (en) * 2003-11-24 2005-06-16 Agilent Technol Inc Two input differential round accumulator

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