JPS55100734A - Output buffer circuit with latch function - Google Patents

Output buffer circuit with latch function

Info

Publication number
JPS55100734A
JPS55100734A JP711979A JP711979A JPS55100734A JP S55100734 A JPS55100734 A JP S55100734A JP 711979 A JP711979 A JP 711979A JP 711979 A JP711979 A JP 711979A JP S55100734 A JPS55100734 A JP S55100734A
Authority
JP
Japan
Prior art keywords
circuit
control signal
circuits
constitution
inverter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP711979A
Other languages
Japanese (ja)
Inventor
Kiyoshi Matsubara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP711979A priority Critical patent/JPS55100734A/en
Publication of JPS55100734A publication Critical patent/JPS55100734A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Abstract

PURPOSE:To simplify the constitution of circuits by letting one circuit function as an inverter constituting a latch circuit and that constituting an inverted push-pull output circuit. CONSTITUTION:With control signal phic at a low level, MISFETQ1 is ON and MISFETQ2 is OFF, so that inverter circuits IN1 and IN2 will take reads prescribed by the input signal level. With control signal phic at a high level, FETQ1 if OFF and Q2 ON, so that circuits IN1 and IN2 will perform holding operation through a positive feedback loop. Since outputs of those circuits IN1 and IN2 are out of phase mutually, they can be used as input control signal for a push-pull output circuit and a latch function provides the constitution of an output buffer circuit. Further, substituting FETQ2 with a high resistance makes it possible to omit inverter circuit IN3 generating control signal phic.
JP711979A 1979-01-26 1979-01-26 Output buffer circuit with latch function Pending JPS55100734A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP711979A JPS55100734A (en) 1979-01-26 1979-01-26 Output buffer circuit with latch function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP711979A JPS55100734A (en) 1979-01-26 1979-01-26 Output buffer circuit with latch function

Publications (1)

Publication Number Publication Date
JPS55100734A true JPS55100734A (en) 1980-07-31

Family

ID=11657188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP711979A Pending JPS55100734A (en) 1979-01-26 1979-01-26 Output buffer circuit with latch function

Country Status (1)

Country Link
JP (1) JPS55100734A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103222A (en) * 1981-12-15 1983-06-20 Nec Corp Flip-flop circuit
JPS6348007A (en) * 1986-08-18 1988-02-29 Nec Corp Flip-flop
JPH05129928A (en) * 1992-04-17 1993-05-25 Hitachi Ltd Semiconductor integrated circuit device
JPH0629830A (en) * 1993-03-22 1994-02-04 Hitachi Ltd Semiconductor integrated circuit device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973062A (en) * 1972-09-28 1974-07-15
JPS5269548A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Flip-flop
JPS53149755A (en) * 1977-03-31 1978-12-27 Toshiba Corp Buffer circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4973062A (en) * 1972-09-28 1974-07-15
JPS5269548A (en) * 1975-12-08 1977-06-09 Hitachi Ltd Flip-flop
JPS53149755A (en) * 1977-03-31 1978-12-27 Toshiba Corp Buffer circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103222A (en) * 1981-12-15 1983-06-20 Nec Corp Flip-flop circuit
JPH0157848B2 (en) * 1981-12-15 1989-12-07 Nippon Electric Co
JPS6348007A (en) * 1986-08-18 1988-02-29 Nec Corp Flip-flop
JPH05129928A (en) * 1992-04-17 1993-05-25 Hitachi Ltd Semiconductor integrated circuit device
JPH0629830A (en) * 1993-03-22 1994-02-04 Hitachi Ltd Semiconductor integrated circuit device

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