JPS56153454A - Spurious signal generating circuit for folding test - Google Patents

Spurious signal generating circuit for folding test

Info

Publication number
JPS56153454A
JPS56153454A JP5762180A JP5762180A JPS56153454A JP S56153454 A JPS56153454 A JP S56153454A JP 5762180 A JP5762180 A JP 5762180A JP 5762180 A JP5762180 A JP 5762180A JP S56153454 A JPS56153454 A JP S56153454A
Authority
JP
Japan
Prior art keywords
bits
register
tag
generating circuit
signal generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5762180A
Other languages
Japanese (ja)
Inventor
Harumasa Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5762180A priority Critical patent/JPS56153454A/en
Publication of JPS56153454A publication Critical patent/JPS56153454A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)

Abstract

PURPOSE:To reduce the scale of hardware monopolized by the test, by operating the tag-in register by encoded information. CONSTITUTION:Tag-in register 16 provided in input/output control device 1 consists of a K-bit flip-flop. Decoder circuit 17 is connected to tag-in register 14, n-bit components of the data line, and P-bit components of the output line of spurious error generating circuit 17 through signal lines. The relation among K bits, n bits, and P bits satisfies K=log2(n+P). If decoder circuit 17 is constituted by the two- input AND gate, n+P gates are sufficient because it decodes K bits. As a result, the number of bits of the flip-flop required in folding tag-in register 16 is reduced considerably.
JP5762180A 1980-04-30 1980-04-30 Spurious signal generating circuit for folding test Pending JPS56153454A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5762180A JPS56153454A (en) 1980-04-30 1980-04-30 Spurious signal generating circuit for folding test

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5762180A JPS56153454A (en) 1980-04-30 1980-04-30 Spurious signal generating circuit for folding test

Publications (1)

Publication Number Publication Date
JPS56153454A true JPS56153454A (en) 1981-11-27

Family

ID=13060938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5762180A Pending JPS56153454A (en) 1980-04-30 1980-04-30 Spurious signal generating circuit for folding test

Country Status (1)

Country Link
JP (1) JPS56153454A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49106203A (en) * 1973-02-08 1974-10-08
JPS5196248A (en) * 1975-02-21 1976-08-24
JPS5250667A (en) * 1975-10-22 1977-04-22 Mitsubishi Electric Corp Trouble checkup method

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49106203A (en) * 1973-02-08 1974-10-08
JPS5196248A (en) * 1975-02-21 1976-08-24
JPS5250667A (en) * 1975-10-22 1977-04-22 Mitsubishi Electric Corp Trouble checkup method

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