JPS57159322A - Information processor - Google Patents

Information processor

Info

Publication number
JPS57159322A
JPS57159322A JP4504481A JP4504481A JPS57159322A JP S57159322 A JPS57159322 A JP S57159322A JP 4504481 A JP4504481 A JP 4504481A JP 4504481 A JP4504481 A JP 4504481A JP S57159322 A JPS57159322 A JP S57159322A
Authority
JP
Japan
Prior art keywords
input
output channel
address
cpu2
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4504481A
Other languages
Japanese (ja)
Inventor
Kunihiro Nagura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP4504481A priority Critical patent/JPS57159322A/en
Publication of JPS57159322A publication Critical patent/JPS57159322A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To increase the accuracy of diagnosis with less additional circuit, by checking an address of a plurality of input and output channels at first connected to a bus with a little additional circuit. CONSTITUTION:When a command to read input and output channel address is incoming from a CPU2 with FFs 34, 44 and 54 reset, the command is interpreted with decoders 32, 42 and 52, and clocks CK1-CK3 are generated. While the clocks CK1-CK3 are zero, the states of the FFs 34, 44 and 54 are checked with gates 33, 43 and 53. If an output OE1 of a gate 22 of an input and output channel 3 goes to 1, the content of the input and output channel address of a switch 35 is outputted to a data line 25. The CPU2 reads the first input and output channel address outputted on the line 25. Then, a signal ENO1 goes to 1 with the leading of the clock CK1 and when an instruction of input and output channel address reading is incoming from the CPU2, the address of an input and output channel 4 is read.
JP4504481A 1981-03-27 1981-03-27 Information processor Pending JPS57159322A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4504481A JPS57159322A (en) 1981-03-27 1981-03-27 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4504481A JPS57159322A (en) 1981-03-27 1981-03-27 Information processor

Publications (1)

Publication Number Publication Date
JPS57159322A true JPS57159322A (en) 1982-10-01

Family

ID=12708359

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4504481A Pending JPS57159322A (en) 1981-03-27 1981-03-27 Information processor

Country Status (1)

Country Link
JP (1) JPS57159322A (en)

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