JPS57162197A - Memory device - Google Patents

Memory device

Info

Publication number
JPS57162197A
JPS57162197A JP56047078A JP4707881A JPS57162197A JP S57162197 A JPS57162197 A JP S57162197A JP 56047078 A JP56047078 A JP 56047078A JP 4707881 A JP4707881 A JP 4707881A JP S57162197 A JPS57162197 A JP S57162197A
Authority
JP
Japan
Prior art keywords
output
signal
strobing
flip
strb1
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56047078A
Other languages
Japanese (ja)
Inventor
Ryuichi Usami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP56047078A priority Critical patent/JPS57162197A/en
Publication of JPS57162197A publication Critical patent/JPS57162197A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To perform the maintenance of a memory device and improve its reliability by generating, holding and informing an error status signal when the value on an output bus is the one other than an expected value at the time other than the output of a data read out from a memory element. CONSTITUTION:When there is no strobing signal STRB1-N at normal operation, all outputs of open collector gates 2-1-1-2-n are ''1''. If the output of any one of the gates 2-1-2-n is fixed on ''0'', the output of a NAND gate 7 is turned to ''1''. Since the output of an AND gate 10 is ''1'' during the non-strobing signal period, a setting signal is generated on the output of the NAND gate 8 by a clock signal and a flip-flip FF11 is set up. Since a strobing signal STRB inputted to an inverter 9 is synchronized with signals STRB1-STRBN, the FF11 is set up and an error status signal is held and sent to a processor.
JP56047078A 1981-03-30 1981-03-30 Memory device Pending JPS57162197A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047078A JPS57162197A (en) 1981-03-30 1981-03-30 Memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047078A JPS57162197A (en) 1981-03-30 1981-03-30 Memory device

Publications (1)

Publication Number Publication Date
JPS57162197A true JPS57162197A (en) 1982-10-05

Family

ID=12765130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047078A Pending JPS57162197A (en) 1981-03-30 1981-03-30 Memory device

Country Status (1)

Country Link
JP (1) JPS57162197A (en)

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