JPS57176458A - Logical device - Google Patents

Logical device

Info

Publication number
JPS57176458A
JPS57176458A JP56061400A JP6140081A JPS57176458A JP S57176458 A JPS57176458 A JP S57176458A JP 56061400 A JP56061400 A JP 56061400A JP 6140081 A JP6140081 A JP 6140081A JP S57176458 A JPS57176458 A JP S57176458A
Authority
JP
Japan
Prior art keywords
gate
output
instruction
inputted
generating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56061400A
Other languages
Japanese (ja)
Inventor
Yoshitaka Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56061400A priority Critical patent/JPS57176458A/en
Publication of JPS57176458A publication Critical patent/JPS57176458A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To make quick evaluation of a hardware and a firmware possible, by generating an interrupting signal only when a specified condition is generated, and generating the competitive state between an asynchronous interruption and an arbitrary instruction as required. CONSTITUTION:An output of a storage circuit 10 setting a cause to asynchronous interruption generated during the execution of an instruction is inputted to an AND gate 61 constituting the interrupting means and another AND gate 61. When the content of an instruction counter 30 and of a designation register is compared, a comparator 50 outputs a signal to open the AND gate 60 only when the content of the both is coincident. An evaluation flip-flop inputs the inverted output to the AND gate 61. The output of the AND gates 60 and 61 is inputted to an AND gate 90 via an OR gate 62.
JP56061400A 1981-04-24 1981-04-24 Logical device Pending JPS57176458A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56061400A JPS57176458A (en) 1981-04-24 1981-04-24 Logical device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56061400A JPS57176458A (en) 1981-04-24 1981-04-24 Logical device

Publications (1)

Publication Number Publication Date
JPS57176458A true JPS57176458A (en) 1982-10-29

Family

ID=13170053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56061400A Pending JPS57176458A (en) 1981-04-24 1981-04-24 Logical device

Country Status (1)

Country Link
JP (1) JPS57176458A (en)

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