JPS56153591A - Failure bit correction system for ic memory - Google Patents

Failure bit correction system for ic memory

Info

Publication number
JPS56153591A
JPS56153591A JP5651480A JP5651480A JPS56153591A JP S56153591 A JPS56153591 A JP S56153591A JP 5651480 A JP5651480 A JP 5651480A JP 5651480 A JP5651480 A JP 5651480A JP S56153591 A JPS56153591 A JP S56153591A
Authority
JP
Japan
Prior art keywords
chip
output
chips
memory
gates
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5651480A
Other languages
Japanese (ja)
Inventor
Nobuaki Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP5651480A priority Critical patent/JPS56153591A/en
Publication of JPS56153591A publication Critical patent/JPS56153591A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE:To increase the operating efficiency of system and to prevent useless chip, by providing the substitution memory chip in place of failed chip in the memory array so that abnormal bits can be reused with correction. CONSTITUTION:When the use of the system is started and the chip selection signals CS1, CS2 designating the chips L0-L7 at left column are output, the chips L0- L7 are simultaneously selected. Further, since the input of both comparison input terminals C1, C2 and C3, C4 of the comparator 3 is all in agreement, the coincidence signal 1 is output from the output terminal CO to select the substitution chip 2. Further, the data read out from the chip L0 in failure is made ineffective with the AND gate 50 in closing and normal data written in the chip 2 is output via the AND gate 60 during opening. On the other hand, the data written in the normal chips L1-L7 is output via the AND gates 51-57 during open, resulting that the accurate data b0-b7 are output from the OR gates 80-87.
JP5651480A 1980-04-28 1980-04-28 Failure bit correction system for ic memory Pending JPS56153591A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5651480A JPS56153591A (en) 1980-04-28 1980-04-28 Failure bit correction system for ic memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5651480A JPS56153591A (en) 1980-04-28 1980-04-28 Failure bit correction system for ic memory

Publications (1)

Publication Number Publication Date
JPS56153591A true JPS56153591A (en) 1981-11-27

Family

ID=13029227

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5651480A Pending JPS56153591A (en) 1980-04-28 1980-04-28 Failure bit correction system for ic memory

Country Status (1)

Country Link
JP (1) JPS56153591A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425264A (en) * 1987-07-22 1989-01-27 Hitachi Ltd Multi chip memory module

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6425264A (en) * 1987-07-22 1989-01-27 Hitachi Ltd Multi chip memory module

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