JPS56110128A - Data transfer system - Google Patents
Data transfer systemInfo
- Publication number
- JPS56110128A JPS56110128A JP1328280A JP1328280A JPS56110128A JP S56110128 A JPS56110128 A JP S56110128A JP 1328280 A JP1328280 A JP 1328280A JP 1328280 A JP1328280 A JP 1328280A JP S56110128 A JPS56110128 A JP S56110128A
- Authority
- JP
- Japan
- Prior art keywords
- register
- data
- processor
- read
- full
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt
Abstract
PURPOSE:To make it possible to exactly transfer a data without requiring many registers, by generating an interruption signal when the transfer register has become vacant after reading it to the processor that said register is full. CONSTITUTION:When a data to be transferred has been generated, a state of the latch FF-1 which has been defined to the address (b) is read. As a result, if it is shown that the FF-1 is vacant, it is possible to write in the register RG, and a data is written in the register RG. On the other hand, when a state of the FF-1 has been read, if it is displayed that the FF-1 is full, the program of the processor P is unable to write a data in the register RG. In this case, the hardware stores by the latch FF- 2 that it has been read into the processor P that the FF-1 is full, and after that, when the register RG has become vacant, an interruption signal I is generated. The program writes a data into the register RG by detecting this interruption.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1328280A JPS5932813B2 (en) | 1980-02-06 | 1980-02-06 | Data transfer method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1328280A JPS5932813B2 (en) | 1980-02-06 | 1980-02-06 | Data transfer method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56110128A true JPS56110128A (en) | 1981-09-01 |
JPS5932813B2 JPS5932813B2 (en) | 1984-08-11 |
Family
ID=11828837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1328280A Expired JPS5932813B2 (en) | 1980-02-06 | 1980-02-06 | Data transfer method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5932813B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154233A (en) * | 1987-12-11 | 1989-06-16 | Toshiba Corp | Interruption processor |
-
1980
- 1980-02-06 JP JP1328280A patent/JPS5932813B2/en not_active Expired
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01154233A (en) * | 1987-12-11 | 1989-06-16 | Toshiba Corp | Interruption processor |
Also Published As
Publication number | Publication date |
---|---|
JPS5932813B2 (en) | 1984-08-11 |
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