JPS6419439A - Central processing unit - Google Patents

Central processing unit

Info

Publication number
JPS6419439A
JPS6419439A JP62177627A JP17762787A JPS6419439A JP S6419439 A JPS6419439 A JP S6419439A JP 62177627 A JP62177627 A JP 62177627A JP 17762787 A JP17762787 A JP 17762787A JP S6419439 A JPS6419439 A JP S6419439A
Authority
JP
Japan
Prior art keywords
register
capability
capability register
address trap
access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62177627A
Other languages
Japanese (ja)
Other versions
JPH0797334B2 (en
Inventor
Yoichi Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62177627A priority Critical patent/JPH0797334B2/en
Publication of JPS6419439A publication Critical patent/JPS6419439A/en
Publication of JPH0797334B2 publication Critical patent/JPH0797334B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To facilitate program debugging by providing an address trap function by the constitution of a capability register and an access control circuit in the computer system provided with an access means which can access data designated by the capability register. CONSTITUTION:A capability register 10 and an access right checking circuit 200 are provided to not only check the access right but also detect an address trap at the time of accessing data through the capability register 10 in case of program execution. Since address trap information is stored in the capability register 10 also, only information in one register is referred to detect the address trap for each object/object model. The number of capability registers 10 which is required for an architecture can be prepared in a central processing unit. Thus, program debugging is facilitated.
JP62177627A 1987-07-15 1987-07-15 Central processing unit Expired - Lifetime JPH0797334B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62177627A JPH0797334B2 (en) 1987-07-15 1987-07-15 Central processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62177627A JPH0797334B2 (en) 1987-07-15 1987-07-15 Central processing unit

Publications (2)

Publication Number Publication Date
JPS6419439A true JPS6419439A (en) 1989-01-23
JPH0797334B2 JPH0797334B2 (en) 1995-10-18

Family

ID=16034308

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62177627A Expired - Lifetime JPH0797334B2 (en) 1987-07-15 1987-07-15 Central processing unit

Country Status (1)

Country Link
JP (1) JPH0797334B2 (en)

Also Published As

Publication number Publication date
JPH0797334B2 (en) 1995-10-18

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