JPS5657153A - Fault detection system - Google Patents

Fault detection system

Info

Publication number
JPS5657153A
JPS5657153A JP13312279A JP13312279A JPS5657153A JP S5657153 A JPS5657153 A JP S5657153A JP 13312279 A JP13312279 A JP 13312279A JP 13312279 A JP13312279 A JP 13312279A JP S5657153 A JPS5657153 A JP S5657153A
Authority
JP
Japan
Prior art keywords
register
detected
giving
information
branch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13312279A
Other languages
Japanese (ja)
Inventor
Itaru Ishikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP13312279A priority Critical patent/JPS5657153A/en
Publication of JPS5657153A publication Critical patent/JPS5657153A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To detect a branch destination error with a small euantity of hardware, by giving an identification number to the word unit of the control memory and by giving double operands to the branch instruction, in the fault detection system of the microprogram control device of the information processor.
CONSTITUTION: Control memory 20 is accessed by information of address register 10, and read information is set to information register 30. The operation code of register 30 is decoded in 80; and if the branch instruction is detected as the result, signal line 80a becomes "1", and the word identification number of the branch destination is stored in register 40. In the next cycle, the micro instruction stored at the address of branch destination is read and stored in register 30. Consequently, when word identification numbers from registers 30 and 40 are compared with each other in 100, signal "0" is ouput to line 100a if agreement is detected; and signal "1" is output to line 100a if disagreement is detected. Thus, the branch destination error can be detected with a small quantity of hardware by giving the identification number to the word unit in the control memory and giving double operands to the branch instruction.
COPYRIGHT: (C)1981,JPO&Japio
JP13312279A 1979-10-16 1979-10-16 Fault detection system Pending JPS5657153A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13312279A JPS5657153A (en) 1979-10-16 1979-10-16 Fault detection system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13312279A JPS5657153A (en) 1979-10-16 1979-10-16 Fault detection system

Publications (1)

Publication Number Publication Date
JPS5657153A true JPS5657153A (en) 1981-05-19

Family

ID=15097296

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13312279A Pending JPS5657153A (en) 1979-10-16 1979-10-16 Fault detection system

Country Status (1)

Country Link
JP (1) JPS5657153A (en)

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