GB2016753A - Data Processing System - Google Patents

Data Processing System

Info

Publication number
GB2016753A
GB2016753A GB7909169A GB7909169A GB2016753A GB 2016753 A GB2016753 A GB 2016753A GB 7909169 A GB7909169 A GB 7909169A GB 7909169 A GB7909169 A GB 7909169A GB 2016753 A GB2016753 A GB 2016753A
Authority
GB
United Kingdom
Prior art keywords
instruction
execution
queue
data
general
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7909169A
Other versions
GB2016753B (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Publication of GB2016753B publication Critical patent/GB2016753B/en
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of GB2016753A publication Critical patent/GB2016753A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)

Abstract

In a data processing system which predecodes and queues a plurality of instructions for sequential presentation to an execution unit, and which includes a plurality of instruction-addressable general registers (56) which can be utilized for temporary data storage or source of address modifying information, an interlock mechanism is provided to detect when an instruction is being decoded which requires use of a general register for address modification, but which general register has not yet received new data by execution of an instruction awaiting execution in the queue (42) of instructions. Two fields (61, 62) are associated with each instruction awaiting execution in the instruction queue. They identify one or more of the general registers to be loaded with data by execution of the instruction. Compare logic (80-83) associated with each register of the instruction queue detects when the general registers identified by the fields in the instruction queue include the general register to be used as address modification data by the instruction presently being decoded. Decoding and address formulation are prevented when the compare exists for any instruction awaiting execution in the queue. <IMAGE>
GB7909169A 1978-03-16 1979-03-15 Data Processing System Withdrawn GB2016753A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88709378A 1978-03-16 1978-03-16

Publications (2)

Publication Number Publication Date
GB2016753B GB2016753B (en)
GB2016753A true GB2016753A (en) 1979-09-26

Family

ID=25390443

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7909169A Withdrawn GB2016753A (en) 1978-03-16 1979-03-15 Data Processing System

Country Status (5)

Country Link
JP (1) JPS54127649A (en)
DE (1) DE2906685A1 (en)
FR (1) FR2420168B1 (en)
GB (1) GB2016753A (en)
IT (1) IT1166667B (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2561429A1 (en) * 1984-03-13 1985-09-20 Trt Telecom Radio Electr ADDRESSING DEVICE FOR PROVIDING MEMORY WITH ADDRESS CODES
EP0159712A2 (en) * 1984-04-27 1985-10-30 Bull HN Information Systems Inc. Control means in a digital computer
EP0205193A2 (en) * 1985-06-17 1986-12-17 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
EP0380850A2 (en) * 1989-02-03 1990-08-08 Digital Equipment Corporation Multiple instruction preprocessing
US5167026A (en) * 1989-02-03 1992-11-24 Digital Equipment Corporation Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
US5488730A (en) * 1990-06-29 1996-01-30 Digital Equipment Corporation Register conflict scoreboard in pipelined computer using pipelined reference counts
US11457671B2 (en) 2019-12-20 2022-10-04 Maddox Holdings Inc. Maternity undergarment for gentle support and shape enhancement

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227829A (en) * 1985-07-30 1987-02-05 Fujitsu Ltd Control system for multiplex load instruction

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477063A (en) * 1967-10-26 1969-11-04 Ibm Controller for data processing system
JPS5320180B2 (en) * 1972-05-09 1978-06-24
JPS5240946B2 (en) * 1972-09-06 1977-10-15
JPS5041442A (en) * 1973-08-16 1975-04-15
JPS5318931A (en) * 1976-08-06 1978-02-21 Hitachi Ltd Information processor

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2561429A1 (en) * 1984-03-13 1985-09-20 Trt Telecom Radio Electr ADDRESSING DEVICE FOR PROVIDING MEMORY WITH ADDRESS CODES
EP0155731A1 (en) * 1984-03-13 1985-09-25 Telecommunications Radioelectriques Et Telephoniques T.R.T. Addressing device for the delivery of address codes to a memory
EP0159712A2 (en) * 1984-04-27 1985-10-30 Bull HN Information Systems Inc. Control means in a digital computer
EP0159712A3 (en) * 1984-04-27 1987-08-05 Honeywell Information Systems Inc. Control means in a digital computer
EP0205193A2 (en) * 1985-06-17 1986-12-17 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
EP0205193A3 (en) * 1985-06-17 1989-09-13 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
EP0380850A2 (en) * 1989-02-03 1990-08-08 Digital Equipment Corporation Multiple instruction preprocessing
EP0380850A3 (en) * 1989-02-03 1991-10-23 Digital Equipment Corporation Multiple instruction preprocessing
US5142631A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register
US5167026A (en) * 1989-02-03 1992-11-24 Digital Equipment Corporation Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
US5488730A (en) * 1990-06-29 1996-01-30 Digital Equipment Corporation Register conflict scoreboard in pipelined computer using pipelined reference counts
US11457671B2 (en) 2019-12-20 2022-10-04 Maddox Holdings Inc. Maternity undergarment for gentle support and shape enhancement

Also Published As

Publication number Publication date
DE2906685A1 (en) 1979-09-20
FR2420168A1 (en) 1979-10-12
IT1166667B (en) 1987-05-06
JPS54127649A (en) 1979-10-03
DE2906685C2 (en) 1988-04-14
GB2016753B (en)
JPS6112289B2 (en) 1986-04-07
IT7920567A0 (en) 1979-02-27
FR2420168B1 (en) 1986-09-26

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee