IT1166667B - ADDRESS FORMULATION INTERLOCK MECHANISM - Google Patents

ADDRESS FORMULATION INTERLOCK MECHANISM

Info

Publication number
IT1166667B
IT1166667B IT20567/79A IT2056779A IT1166667B IT 1166667 B IT1166667 B IT 1166667B IT 20567/79 A IT20567/79 A IT 20567/79A IT 2056779 A IT2056779 A IT 2056779A IT 1166667 B IT1166667 B IT 1166667B
Authority
IT
Italy
Prior art keywords
interlock mechanism
address formulation
formulation
address
interlock
Prior art date
Application number
IT20567/79A
Other languages
Italian (it)
Other versions
IT7920567A0 (en
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of IT7920567A0 publication Critical patent/IT7920567A0/en
Application granted granted Critical
Publication of IT1166667B publication Critical patent/IT1166667B/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818—Decoding for concurrent execution
    • G06F9/3822—Parallel decoding, e.g. parallel decode units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
IT20567/79A 1978-03-16 1979-02-27 ADDRESS FORMULATION INTERLOCK MECHANISM IT1166667B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US88709378A 1978-03-16 1978-03-16

Publications (2)

Publication Number Publication Date
IT7920567A0 IT7920567A0 (en) 1979-02-27
IT1166667B true IT1166667B (en) 1987-05-06

Family

ID=25390443

Family Applications (1)

Application Number Title Priority Date Filing Date
IT20567/79A IT1166667B (en) 1978-03-16 1979-02-27 ADDRESS FORMULATION INTERLOCK MECHANISM

Country Status (5)

Country Link
JP (1) JPS54127649A (en)
DE (1) DE2906685A1 (en)
FR (1) FR2420168B1 (en)
GB (1) GB2016753A (en)
IT (1) IT1166667B (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2561429B1 (en) * 1984-03-13 1986-09-19 Trt Telecom Radio Electr ADDRESSING DEVICE FOR PROVIDING ADDRESS CODES TO A MEMORY
FI86484C (en) * 1984-04-27 1992-08-25 Honeywell Inf Systems STYRORGAN I EN DIGITAL DATAMASKIN.
US4777592A (en) * 1985-06-17 1988-10-11 Nec Corporation Information processing system comprising a register renewal waiting control circuit with renewal register number registering means
JPS6227829A (en) * 1985-07-30 1987-02-05 Fujitsu Ltd Control system for multiplex load instruction
US5142631A (en) * 1989-02-03 1992-08-25 Digital Equipment Corporation System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register
US5167026A (en) * 1989-02-03 1992-11-24 Digital Equipment Corporation Simultaneously or sequentially decoding multiple specifiers of a variable length pipeline instruction based on detection of modified value of specifier registers
DE69130138T2 (en) * 1990-06-29 1999-05-06 Digital Equipment Corp Jump prediction unit for high-performance processor
US5432918A (en) * 1990-06-29 1995-07-11 Digital Equipment Corporation Method and apparatus for ordering read and write operations using conflict bits in a write queue
US5471591A (en) * 1990-06-29 1995-11-28 Digital Equipment Corporation Combined write-operand queue and read-after-write dependency scoreboard
US5450555A (en) * 1990-06-29 1995-09-12 Digital Equipment Corporation Register logging in pipelined computer using register log queue of register content changes and base queue of register log queue pointers for respective instructions
US11457671B2 (en) 2019-12-20 2022-10-04 Maddox Holdings Inc. Maternity undergarment for gentle support and shape enhancement

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477063A (en) * 1967-10-26 1969-11-04 Ibm Controller for data processing system
JPS5320180B2 (en) * 1972-05-09 1978-06-24
JPS5240946B2 (en) * 1972-09-06 1977-10-15
JPS5041442A (en) * 1973-08-16 1975-04-15
JPS5318931A (en) * 1976-08-06 1978-02-21 Hitachi Ltd Information processor

Also Published As

Publication number Publication date
DE2906685C2 (en) 1988-04-14
JPS6112289B2 (en) 1986-04-07
IT7920567A0 (en) 1979-02-27
JPS54127649A (en) 1979-10-03
DE2906685A1 (en) 1979-09-20
FR2420168A1 (en) 1979-10-12
FR2420168B1 (en) 1986-09-26
GB2016753A (en) 1979-09-26
GB2016753B (en)

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