JPS6112289B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to predecoding a plurality of system instructions, and more particularly, to predecoding system instructions using general purpose registers that have not yet been loaded by decoded and unexecuted instructions. This relates to preventing the formation of instruction addresses.

The present invention can be applied to high-performance data processing systems, for example, in the publication "IBM System/370, Principles of
GA22-7000). Sixteen general purpose registers in these data processing systems are addressable by instructions and are used for temporary storage of data or for address calculations. In the latter case, the selected general purpose register holds a base address or address index value that is added to the address information in the instruction to be executed.

U.S. Patent No. 4,200,927 describes a data processing system according to the IBM System/370 specifications,
More particularly, an instruction preprocessing unit is disclosed that is capable of stacking or queuing predecoded instructions for sequential transfer to an execution unit. Instructions waiting to be executed on this instruction queue may specify a general-purpose register to receive new data, so subsequent instructions must use this same general-purpose register to form main memory addresses. If so, decoding of the subsequent instruction in the instruction register must be inhibited.

The IBM System/370 has several instructions that modify the contents of general purpose registers. These instructions specify one general-purpose register into which data should be loaded using the "R1 field." The data to be loaded into this general purpose register R1 comes from another general purpose register, some main memory location, or the output of an arithmetic unit. Certain instructions that specify general-purpose register R1 specify general-purpose register R1+1
may also implicitly specify that it should also be loaded. Further, a load instruction specifies accessing multiple main memory locations and loading the contents of the locations into a set of general purpose registers starting with general purpose register R1 and ending with general purpose register R3. This specific instruction is called a LOAD MULTIPLE instruction.

Representative high-performance data processing systems similar to those disclosed in the above-mentioned U.S. patents include IBM Systems/
370 model 168, the instruction preprocessing unit of this computer operates to prefetch, predecode, stack or queue a plurality of instructions, and then sequentially provide these instructions to the execution unit. This instruction preprocessing unit is described in the publication “System/370 Model 168,” published by IBM.
Theory of Operations, Diagrams Manual
(Vol.2), I-Unit” (Form No.SY22-6932-
3).

In this prior art computer, whenever an instruction that modifies the contents of a general-purpose register is decoded and placed in the instruction queue, the identifier of general-purpose register R1 is placed in the instruction queue register along with the instruction execution information to be provided to the execution unit. will be filled in. In situations where this general purpose register R1 is needed for the address calculation of a subsequent instruction, this information can be used to effectively prevent decoding of the subsequent instruction. However, since the multiple load instruction specifies a set of general-purpose registers from general-purpose registers R1 to R3, the information regarding R1 mentioned above means that the subsequent instruction being decoded will
It is not possible to detect situations such as requiring a general purpose register with an identifier larger than R1. Thus, in this prior art computer, whenever a load multiple instruction is decoded and placed into the instruction queue, subsequent instructions are It was done to prohibit decoding.

SUMMARY OF THE INVENTION During use of the IBM System/370 Model 168, it has been discovered that multiple load instructions are used more frequently than expected. It is easy to see that if instruction predecoding had to be stopped every time a multiple load instruction is decoded, the efficiency of the system would be significantly reduced.

A primary objective of the present invention is to allow pre-decoding and queuing of each instruction following decoding and queuing of multiple load instructions that modify multiple general purpose registers.

Another object of the invention is to provide one general purpose register, one
The object is to provide address forming interlock logic that is sufficiently generalized to accommodate paired general purpose registers, load instructions that specify more than one general purpose register in a region.

The above objectives are accomplished by providing two general purpose register specification fields to each predecoded instruction entered into the instruction queue.
Each instruction queue register location has an associated compare circuit. This comparison circuit compares the general register designation field of the instruction being decoded, which is used as base address information or address index information, with the two general register designation fields. The comparison circuit is sufficiently generalized to accommodate three types of load instructions that specify one, a pair, or an area of general-purpose registers, so that the comparison logic must be used before placing the information in the instruction queue. Given. Additionally, the multiple load instruction may specify a starting general register (R1) having a larger value than an ending general register (R3). Additionally, the comparison logic is adapted to provide the correct interlock when it occurs.

DISCLOSURE OF THE INVENTION FIG. 1 shows the main functional parts of a high performance data processing system. The invention resides in the instruction preprocessing function unit (IPPF) 20. IPPF 20 communicates with a processor storage control function unit (PSCF) 21, which includes a high-speed buffer or cache, to retrieve a sequence of instructions from processor storage 22 and initiate the transfer of data operands to an execution unit or E function unit 23. Furthermore, the IPPF 20 communicates with the E function unit 23 and sequentially transfers one instruction at a time to the E function unit 23. The result of the instruction execution in the E function unit 23 is the IPPF2
By returning it to 0, the execution of a series of instructions is controlled. The remaining portions of the data processing system which are not critical to an understanding of the invention include the channel 24, the control console 25, and the "maintenance and retry" control unit 26.

FIG. 2 shows four main functional areas in the IPPF 20 of FIG. These areas include three instruction stream prefetch logic sections 27, an instruction predecode section 28 (both of which are described in detail in the aforementioned US patent), an address formation logic section 29, and an interlock mechanism which is the subject of the present invention. Includes portion 30. IPPF 20 has the ability to store (ie, queue) four predecoded instructions and sequentially provide them to destination E functional unit 23, one at a time. The IPPF 20 contains information regarding the data operands to be fetched, the general purpose registers to be used, the starting address information for microprogram control storage, and various control signals to be described in detail below. The majority of instructions to be decoded require address operations to be performed in the IPPF 20, and therefore an address formation logic section 29 is provided. Interlock mechanism section 30 is required to ensure that the correct data is available for use in address formation and instruction pre-decoding before placing decoded instruction information into the four-position queue.

In FIG. 3, instruction buffer register 3
1, 32, and 33 are shown. When one instruction buffer register is selected, it receives 64 bits of instruction information each time an instruction fetch request signal is transferred to PSCF 21. Thirty-two 8-bit bytes of instruction information can be prefetched and stored in each of instruction buffer registers 31, 32, and 33.

In the disclosed system, the command is IPPF2
If it is 0, it will be decoded to one address at 1 o'clock. The specific instructions to be decoded are stored in the I register 3 in the appropriate order.
Transferred to 5. I register 35 contains 32 bits of instruction information. During the execution of an instruction, various gates indicated at 36 are used to transfer a suitable one of a plurality of instructions from one of the instruction buffer registers currently in use to the I register 35 for decoding. Energized according to counter address information. The gate group 36 has instructions for IBM System/360 and System/370 of variable length (2, 4
(6 8-bit bytes), so it must be compatible with that. For each instruction to be decoded, 8 bits of the operational code are placed in bit position 0 of I register 35.
To ensure placement at ~7, various gates are activated in combination. Depending on the format of the particular instruction being decoded in the I register 35, bits 8-15 of that register may be mask bits, encoded information regarding the length of a variable length field operand, or may be a general purpose bit. May be the address of a register. Bit 12
-15 and 16-19 may specify a particular one of the 16 general purpose registers according to address formation methods in the IBM System/360 and System/370. Bits 20-31 in the 4-byte instruction are address displacement fields, which are used to form address information when accessing data operands in storage.

The instruction decoding mechanism of IPPF 20 includes a hardware decoder 37, an array decoder 38, and a control storage address register (CSAR) decoder 39. Decoding each instruction in I register 35 requires two clock cycles in the system.
On the first clock cycle, some information about the instruction being decoded must be made available as soon as possible. This information is provided via a hardware decoder 37. It is not known whether other information is needed until the second cycle of instruction decoding. This information is obtained from array decoder 38. There, operational code bits 0-7 are used to address the random access array and provide outputs on a plurality of control signal lines 40 and 41.

The result of the instruction decoding described above is stored in one of the four registers of the instruction queue 42 as instruction execution control information. Part of the execution control information is line 4
3, which are 8 bits of operational code indicating the basic functions to be performed by the execution unit. In many known microprogram control systems, eight operational code bits are used to address the first microinstruction in a series of microinstructions for instruction execution. To increase the efficiency of the microprogram control system, another binary bit is provided on line 44 which is utilized in the first cycle when accessing control storage. Line 44 extends from CSAR decoder 39 which is responsive to mask information in bit positions 8-15 of the instruction being decoded and control signals on line 41 obtained from array decoder 38. Other additional execution control information is obtained on line 40 from array decoder 38. Line 45 represents operand address information obtained from address formation logic 29 (FIG. 2). Execution control information in the four registers of instruction queue 42 is transferred to E functional unit 23 for respective execution.

Prefetching instructions A, B, and C of a specific instruction sequence into a specific one of the instruction buffer registers 31 to 33 involves providing one instruction to the I register 35 and sending execution control information to the instruction queue 42. This occurs in parallel with filling an empty one of the four registers in the register. In order to sequentially gate the next instruction execution control information from one of the four registers in the instruction queue 42 to the E functional unit 23 and execute the instruction, a signal indicating completion of instruction execution is given from the E functional unit. . As long as empty registers are available in instruction queue 42, decoding of instructions and placing execution control information into instruction queue 42 will continue to occur.

In addition to suspending instruction decoding because all four registers in instruction queue 42 are filled, other machine conditions, broadly classified as interlocks, suspend instruction decoding. As part of the instruction decoding process, the storage address is determined by combining the address bits contained in the instruction with data in general purpose registers addressable by the instruction, as is done on the IBM System/360 and System/370. It is formed. If the instruction contained in the instruction queue 42 has not yet been executed and this instruction is to load information into a general-purpose register used to form the address of the instruction currently contained in the I register 35, instruction decoding is prohibited. Otherwise, an interrupting interlock mechanism must be activated. In this case, instruction decoding in the I register 35 must be suspended until information is provided from the yet-to-be-executed instruction.

The IBM System/360 and System/370 specify general purpose registers that are addressable by an instruction. These general purpose registers are usually E functional unit 2.
Physically located in 3. Furthermore, a second group of 16 general-purpose registers is included in the IPPF 20 to speed up address calculations. These are indicated at 46 in FIG. The normal path for entering information into general purpose register group 46 is through a working register labeled C-REG, with information being entered into general purpose register group 46 from line 47. line 4
8 and 49 are general-purpose registers from I register 35.
Receive address information. The output of general purpose register group 46 is applied to address adder 52 along with displacement address bits 20-31 sent via lines 53 from I register 35.

FIG. 4 shows an I register 35, an array decoder 3
8. Instruction queue 42 (only one copy) is shown. All of these are shown in FIG. As previously mentioned, as part of the instruction decoding process, operational code bits 0-7 are transferred from the I register 35 to the array decoder 3.
8 to generate a control signal. Two control signals are generated on lines 54 and 55 which indicate which of the general purpose registers a store is to be made.

The I register 35 in FIG. 4 shows the format of a multiple load (LM) instruction. General purpose register group 56 must be loaded sequentially, starting with the register specified by field R1 and continuing to the register specified by field R3. The main memory address of the first operand loaded into register R1 utilizes the displacement address bit (D2). D2 bit is field
General purpose register (base register) specified by B2
is added to the address bits contained in the address bit. A load occurs as shown at 57 when field R1 specifies a general purpose register that is equal to or less than the general purpose register specified by field R3. Additionally, the general purpose register in field R1 may be larger than the general purpose register indicated by field R3, in which case the register loading starts with register R1, proceeds through the last general purpose register to the first general purpose register, and then loads the registers to register R3. leading to.

In FIG. 4, only a portion of each register of instruction queue 42 is shown. That is, to aid in understanding the invention, only those portions of the registers that generate the appropriate address formation interlocks are shown. Much instruction execution control information is placed into each register of instruction queue 42 for later provision to the execution unit. Register 60 (Q0) is “GR
4-bit field 61 labeled "GR HIGH" and a 4-bit field 62 labeled "GR HIGH". When an instruction is decoded from the I register 35, execution control information is placed into a register of the instruction queue 42 according to an pointer that points to the next empty queue register location. When information is placed into that register, the inpointer is stepped to the next empty register and the register that received the execution information has its associated busy trigger turned on. A busy trigger on indicates that valid information is contained in that register.

In response to control signals on lines 54 and 55 coming from array decoder 38, register change decoder 63 provides gate control signals on lines 64, 65, and 66. This indicates that an instruction that changes the contents of a particular general purpose register has been decoded in I register 35. When control signal lines 54 and 55 have a code of 00, the general registers are not modified and therefore fields 61 and 62 remain in the reset state (0).
The value of the). For other codes, field 61 is always set to the value of field R1 by activation of gate 67, and the value of R1 is placed via line 68 into field 61 of the instruction queue register which receives the decoded information. It will be done.

Field 62 of the instruction queue register, which receives the decoded information, is set by the input on line 69 coming from OR circuit 70. OR circuit 7
0 receives input from lines 71, 72, 73. Line 72 provides information to field 62 when the gate is energized by signal line 64 and only R1 is to be loaded. For an instruction, when R1 is loaded, if it indicates an even numbered register, it means that the next register R1+1 should also be loaded. The value of R1 is increased by 1 in the intensifier 74;
A gate 75 provides an OR circuit 70.
To increment a 1, simply force the low order bit of R1 (always a 0) to a binary 1. If a multiple load instruction is decoded, gate 76 is connected to line 6.
6, the value of R3 is placed in field 62.

In association with each of the registers 60, 77, 78, 79, a corresponding comparison circuit 80, 81, 82, 83
is provided. Each of comparator circuits 80-83 is enabled by a signal line 84 from an associated busy trigger when the queue register location contains valid instruction execution information. To provide interlock information, the contents of fields 61 and 62 in the busy queue register location are compared to the instruction being decoded in I register 35 (only a portion of which is shown at 85, 86). This instruction forms an address using the contents of a designated general-purpose register. The instruction fields involved in address formation are 85 and 8, respectively.
6 are B2 and X2. B2 specifies the general-purpose register containing the base address value, and X2 specifies the general-purpose register containing the address index value. Above 2
The value is added to the displacement address (12 binary bits) in the instruction field D2.

When the X2 field or B2 field of the instruction being decoded is incompatible (conflicts) with the values contained in fields 61 and 62 in any instruction queue register by any of the comparator circuits 80-83, the associated Comparison circuit line 87
(indicating X field incompatibility) or 88 (B
A signal is generated on the field (indicating the incompatibility of the field) to indicate the incompatibility.

FIG. 5 shows details of the comparator circuit 80 associated with the queue register 60. When the decoding of an instruction is complete and the information is to be placed in the instruction queue 42 (Figure 3), that information is indicated by the inpointer value on the line 89 (Figure 5) associated with the instruction queue. placed in the instruction queue location. R1
The value of is entered into field 61 and field 6
2 receives either R1, R1+1, or R3. The 4-bit B2 and X2 fields are provided to the comparator circuit by lines 85 and 86 for comparison with fields 61 and 62 of all instruction queue register locations.

The function of comparator circuit 80 is to detect when the general purpose register specified by the X2 field or B2 field of the instruction being decoded falls within the shaded area of FIG. As shown by general purpose register group 56 in FIG. 4, two different states occur depending on the values of R1 and R3. Comparator circuit 90 in FIG. 5 receives the values of R1 and R3, and inverter 9
1 on line 92. The binary state of this signal distinguishes when R1 is greater than or less than R3. The remaining comparison circuits 93 to 96 are
The R1 and R3 values contained in the fields 61 and 62, respectively, are compared with the values of the X2 field and the B2 field, and an output signal indicating that they are greater, smaller, or equal is provided. OR circuits 97 and 98 provide signals indicating incompatible conditions. If the positive output signal on line 92 indicates that R1 is greater than R3, then
AND circuits 99, 100, 101, and 102 provide signals indicating that the B2 field or the X2 field is within the shaded area 58 or 59 of FIG. When the above field is within the shaded region 57 of FIG. 4, AND circuits 103 and 103a are satisfied to provide an incompatible signal.

FIG. 6 shows the ultimate object of the invention. That is,
When an incompatible condition exists, OR circuit 104 provides a decode disturb output signal on line 105. This signal inhibits complete decoding of the instruction in the I register 35 (FIGS. 3 and 4). The instruction in instruction queue 42 that established the incompatibility condition must be completely executed and cleared from the instruction queue before decoding of instructions in I register 35 can resume. OR circuit 106 provides an output signal when there is an incompatible condition for the B2 field, and OR circuit 107 provides an output signal when there is an incompatible condition for the X2 field.

Any of the comparator circuits 80-83 may provide a signal indicating an incompatible condition, but two other conditions must be met. The first condition is IBM System/370
Regarding the definition of design philosophy. This definition means that when the B2 field and the X2 field contain the value 0,
These fields shall not specify general-purpose registers involved in address formation. Therefore, the sixth
The illustrated zero detection circuits 108 and 109, via associated inverters 110 and 111, indicate whether these fields contain a zero value.

The second condition relates to lines 112 and 113 in FIG. On those lines are the control signal outputs from the array decoder 38 of FIGS. 3 and 4. These lines indicate that the instruction being decoded in I register 35 has a B2 field or an X2 field. When these two conditions are met, AND circuits 114 and 115 typically
A group of AND circuits designated 6 and 117 are activated. These AND circuits provide two signals indicating that the associated queue (Q) register is busy (84) and that the associated queue register's comparator circuit is signaling an incompatible condition (87, 88). Has input.

FIG. 7 shows comparison circuits 90, 9 shown in FIG.
3, 94, 95, and 96 are shown in detail. OR
When any of the AND circuits providing input to circuit 119 is activated, a positive output signal is output to OR circuit 11.
9 on line 118. For example, AND
When circuit 120 receives a positive signal from AND circuit 121, it provides a positive signal to OR circuit 119. AND circuit 121 is Z (field 62)
The high-order bit position 0 of is a binary 1, and Y
This shows that the high-order bit position 0 of (field 61) is a binary 0. This indicates that Y is smaller than Z. Three subsequent AND circuits providing input to OR circuit 119 detect when the high order binary bits of Y and Z are equal and the next low order binary bit makes Y less than Z. Finally, AND circuit 1
22 provides an output when the value of Y is equal to the value of Z.

Figures 8, 9, and 10 illustrate the decoding of an instruction when the instruction may request to use the contents of a general-purpose register that has not yet been loaded by a previous instruction. FIG. 3 is a timing diagram illustrating the differences between the present invention and the prior art with respect to the generation of a jamming signal. Waveform 123 in FIG. 8 shows the timing of one machine cycle. This timing is such that when an instruction is being decoded, the decode and address operation (D/
A) is designed to be completed in one machine cycle. FIG. 8 shows the decoding of a load instruction in which general register R1 is modified. The access timing of the storage mechanism is such that instruction execution is completed at 125;
Data is to be inserted into register R1 at 126. The value of R1 is ingated at 127 into the queue register location Q _o pointed to by the inpointer. The busy trigger associated with _Qo is turned on for 128 hours. The consecutive instructions are decoded at a rate such that one instruction is decoded and the address operation is completed in one cycle. Therefore, as shown in Figure 8, the STORE instruction is decoded.
If X2 field is equal to R1, then R1 is at time 12
Decoding is prevented until cleared from Q _o at 9. At time 129, the incompatibility indicated at 130 is removed and the decoding and address operation of the store instruction occurs at 131.

FIG. 9 shows a case where a multiple load instruction specifying R1 and R3 is decoded at 132. Q _o is 1
33 is indicated as busy. According to the prior art, recognition of multiple load instructions interferes with store instruction decoding and address operations even when the next instruction to be decoded uses an X2 field or a B2 field that is not equal to R1-R3. The decoding and address operation of the next store instruction at 135 does not occur until the data is finally placed in R3 at 134.

FIG. 10 shows that in accordance with the present invention, a multiple load instruction is decoded at 136 and the R1 and R3 fields are placed in the queue register location Q as shown at 137.
Indicates the capabilities of a data processing system when ingested into _o . Queue register location Q _o is shown as busy as before. In accordance with the present invention, the next store instruction decode and address operation is allowed to occur at 138 when neither the X2 field nor the B2 field is in the R1-R3 value range. The instruction control information obtained as the decoding and address operations proceed is transferred to the queue register location Q _o +1 indicated by the inpointer.
will be forwarded to. When the next store instruction that _requires an and address operations are prevented until such time as indicated at 139, for example, that Q _o is no longer busy.

According to the present invention, the decoding and address formation of instructions following a multiple load instruction is 138 when the X and B fields are not equal to R1 to R3.
It will be understood from FIG. 10 that this can be done. According to the prior art, decoding of the next instruction cannot occur until after the multiple load instruction has been completely executed, as shown at 135 in FIG.

[Brief explanation of drawings]

Figure 1 is a block diagram of the main functional parts of the data processing system, Figure 2 is a block diagram showing details of the instruction preprocessing function, and Figure 3 is the instruction preprocessing function showing instruction decoding, address formation, and instruction queuing. 4 is a block diagram showing a functional unit that controls multiple load instructions to place general register designation information into appropriate fields of the instruction queue; FIG. 5 is a block diagram showing the instruction queue and the instructions being decoded. a logic diagram of a comparison circuit that receives input from general-purpose register designation information in the field;
FIG. 6 is a logic diagram that responds to an incompatibility between a general register field in an instruction queue and a general register field in an instruction to be decoded to prevent subsequent decoding; FIG. 8, 9, and 10 are timing diagrams illustrating the differences between the interlock logic of the prior art and the interlock logic of the present invention. It is. 31, 32, 33...Instruction buffer register, 35...Instruction () register, 37...Hardware decoder, 38...Array decoder, 39...
...Control storage address register decoder, 42...
Instruction queue, 46...General-purpose register group, 52...
Address adder, 56...General-purpose register group, 60
...Register, 63...Register change decoder, 6
7, 75, 76...gate, 80, 81, 82,
83... Comparison circuit.

Claims (1)

[Scope of Claims] 1. An instruction queue comprising an instruction register, an instruction decoder for decoding instructions placed in the instruction register, and a plurality of queue registers for storing execution control information for the decoded instructions,
In an instruction pre-processing unit that can form a main memory address from address information in an instruction and address information in a general-purpose register specified by the instruction when pre-decoding an instruction: first and second general purpose register identifiers disposed in each of said queue registers to store second general purpose register designation information; responsive to a decoded instruction requesting a load into at least one general purpose register; The designation information of the first general-purpose register and the last general-purpose register to be loaded (in the case of one general-purpose register, the designation information) is stored in the first and second general-purpose registers in the queue register selected from the instruction register. gate means for respectively transferring data to the general-purpose register identification sections; a plurality of comparison means provided corresponding to the queue registers; and storage in the first and second general-purpose register identification sections in each of the queue registers. means for respectively connecting first and second general-purpose register designation information corresponding to the queue register to one input of the set of comparison means; at least one general-purpose register among the instructions placed in the instruction register; means for respectively connecting register designation information, which is designation information of a general-purpose register to be used to form the main memory address, to the other input of the plurality of sets of comparison means; and signal means for inhibiting subsequent operations of the instruction decoder in response to the plurality of comparison means for detecting that the instruction decoder is within the range of the first or second general register designation information.