JPS6438834A - Information processor - Google Patents
Information processorInfo
- Publication number
- JPS6438834A JPS6438834A JP19559987A JP19559987A JPS6438834A JP S6438834 A JPS6438834 A JP S6438834A JP 19559987 A JP19559987 A JP 19559987A JP 19559987 A JP19559987 A JP 19559987A JP S6438834 A JPS6438834 A JP S6438834A
- Authority
- JP
- Japan
- Prior art keywords
- operand
- buffer
- instruction
- abnormality
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE:To surely detect the abnormality of an operand buffer by using a phenomenon that contents of the operand buffer and those of an instruction discrimination code buffer are different from each other in case of the occurrence of abnormality in the read/write control of the operand buffer. CONSTITUTION:An operand is correctly read out from a storage unit 20 by an operand address 61 correctly generated by an operand address generating circuit 11, and an obtained operand 70 is written in an operand buffer 30. Meanwhile, an instruction ID 62 generated by an instruction ID generating circuit 12 is synchronized with the operand 70 by a register 13 and is written in not only the buffer 30 but also an instruction ID buffer 31. When an arithmetic processing unit 40 starts the processing, the instruction ID is set to a register 32 through registers 13 and 14 independently of a bus to the buffer 31 and the instruction ID corresponding to the operand is read out from the buffer 31 and is set to a register 33, and coincidence between them is checked by a comparator 34. If abnormality is detected, an abnormal state signal 50 is outputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19559987A JPS6438834A (en) | 1987-08-04 | 1987-08-04 | Information processor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19559987A JPS6438834A (en) | 1987-08-04 | 1987-08-04 | Information processor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6438834A true JPS6438834A (en) | 1989-02-09 |
Family
ID=16343831
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19559987A Pending JPS6438834A (en) | 1987-08-04 | 1987-08-04 | Information processor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6438834A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207238A (en) * | 2006-02-02 | 2007-08-16 | Internatl Business Mach Corp <Ibm> | Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline |
-
1987
- 1987-08-04 JP JP19559987A patent/JPS6438834A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007207238A (en) * | 2006-02-02 | 2007-08-16 | Internatl Business Mach Corp <Ibm> | Apparatus and method for handling data cache miss out-of-order for asynchronous pipeline |
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