JPS649561A - Computer - Google Patents

Computer

Info

Publication number
JPS649561A
JPS649561A JP62165610A JP16561087A JPS649561A JP S649561 A JPS649561 A JP S649561A JP 62165610 A JP62165610 A JP 62165610A JP 16561087 A JP16561087 A JP 16561087A JP S649561 A JPS649561 A JP S649561A
Authority
JP
Japan
Prior art keywords
data
cpu
data bus
width
checking
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62165610A
Other languages
Japanese (ja)
Inventor
Noriyoshi Otsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP62165610A priority Critical patent/JPS649561A/en
Publication of JPS649561A publication Critical patent/JPS649561A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4009—Coupling between buses with data restructuring
    • G06F13/4018—Coupling between buses with data restructuring with data-width conversion

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To provide complete interchangeability on a software by checking the data width on a data bus so as to control the data processing speed of a CPU depending on the size, thereby operating the computer system having the same internal data processing unit but using CPUs with different data bus width timewise entirely identically. CONSTITUTION:The titled computer is provided with a storage element 2 storing information such as a program, a CPU 1, a data bus 6 giving/receiving a data with the element 2, a word data detecting circuit 7 checking the data width on the data bus 6, and a speed control circuit 8 controlling the processing speed of the CPU 1 depending on the signal generated from the word data detecting circuit 7. Thus, the CPU having the same data processing unit but different data bus width is operated at any time in the same timing to provide the complete interchangeable to the software.
JP62165610A 1987-07-02 1987-07-02 Computer Pending JPS649561A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62165610A JPS649561A (en) 1987-07-02 1987-07-02 Computer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62165610A JPS649561A (en) 1987-07-02 1987-07-02 Computer

Publications (1)

Publication Number Publication Date
JPS649561A true JPS649561A (en) 1989-01-12

Family

ID=15815633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62165610A Pending JPS649561A (en) 1987-07-02 1987-07-02 Computer

Country Status (1)

Country Link
JP (1) JPS649561A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594877A (en) * 1992-03-18 1997-01-14 Seiko Epson Corporation System for transferring data onto buses having different widths
WO2008053980A1 (en) * 2006-10-27 2008-05-08 Panasonic Corporation Cryptographic method and apparatus for enhancing computation performance of a central processing unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5594877A (en) * 1992-03-18 1997-01-14 Seiko Epson Corporation System for transferring data onto buses having different widths
WO2008053980A1 (en) * 2006-10-27 2008-05-08 Panasonic Corporation Cryptographic method and apparatus for enhancing computation performance of a central processing unit
US8204219B2 (en) 2006-10-27 2012-06-19 Panasonic Corporation Cryptographic method and apparatus for enhancing computation performance of a central processing unit

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