JPS644841A - In-circuit emulator - Google Patents

In-circuit emulator

Info

Publication number
JPS644841A
JPS644841A JP62161597A JP16159787A JPS644841A JP S644841 A JPS644841 A JP S644841A JP 62161597 A JP62161597 A JP 62161597A JP 16159787 A JP16159787 A JP 16159787A JP S644841 A JPS644841 A JP S644841A
Authority
JP
Japan
Prior art keywords
data
control cpu
arbitrary
microprocessor
target microprocessor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62161597A
Other languages
Japanese (ja)
Other versions
JP2575025B2 (en
Inventor
Yoshio Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP62161597A priority Critical patent/JP2575025B2/en
Publication of JPS644841A publication Critical patent/JPS644841A/en
Application granted granted Critical
Publication of JP2575025B2 publication Critical patent/JP2575025B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To execute an I/O simulation of an arbitrary data by setting a target microprocessor to a waiting state, when a target microprocessor has executed an access to an I/O data, and in this case, sending and receiving an arbitrary I/O data by a control CPU. CONSTITUTION:The titled emulator is provided with an I/O address detecting circuit 3, a wait generating circuit 4, a means for allowing a control CPU 5 to read an address bus, a status and data bus information of a microprocessor 1, when the target microprocessor 1 has become a waiting state, and an I/O event memory 6 in which simulation information of an I/O is stored, and which is brought to an access from the control CPU 5. When the target microprocessor 1 has executed an access to the I/O address, the target microprocessor 1 is set to a waiting state, and in this case, an arbitrary I/O data is sent and received by the control CPU 5. In such a way, an I/O simulation of an arbitrary data can be executed.
JP62161597A 1987-06-29 1987-06-29 In-circuit emulator Expired - Lifetime JP2575025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62161597A JP2575025B2 (en) 1987-06-29 1987-06-29 In-circuit emulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62161597A JP2575025B2 (en) 1987-06-29 1987-06-29 In-circuit emulator

Publications (2)

Publication Number Publication Date
JPS644841A true JPS644841A (en) 1989-01-10
JP2575025B2 JP2575025B2 (en) 1997-01-22

Family

ID=15738169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62161597A Expired - Lifetime JP2575025B2 (en) 1987-06-29 1987-06-29 In-circuit emulator

Country Status (1)

Country Link
JP (1) JP2575025B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007241616A (en) * 2006-03-08 2007-09-20 Nec Corp Chip set emulation device and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007241616A (en) * 2006-03-08 2007-09-20 Nec Corp Chip set emulation device and method

Also Published As

Publication number Publication date
JP2575025B2 (en) 1997-01-22

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