JPS57146353A - Program executing state recording system in multiprocessor system - Google Patents

Program executing state recording system in multiprocessor system

Info

Publication number
JPS57146353A
JPS57146353A JP56030711A JP3071181A JPS57146353A JP S57146353 A JPS57146353 A JP S57146353A JP 56030711 A JP56030711 A JP 56030711A JP 3071181 A JP3071181 A JP 3071181A JP S57146353 A JPS57146353 A JP S57146353A
Authority
JP
Japan
Prior art keywords
information
processor
recording
memory
recorder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56030711A
Other languages
Japanese (ja)
Inventor
Hajime Saito
Naoki Yamada
Toshio Yajima
Fumito Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP56030711A priority Critical patent/JPS57146353A/en
Publication of JPS57146353A publication Critical patent/JPS57146353A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/36—Preventing errors by testing or debugging software

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To make program debugging easy, by grasping the timing state of execution of information processing for processors in a multiprocessor system through the recording of program execution and access state in time division to a recorder sequentially. CONSTITUTION:A recording memory of a recorder records a signal outputted from a scan circuit N in 1/n of the shortest instruction executing time of each processor together with a processor number, i.e., program address number information, instruction information and read/write information and the like. A trace signal generated at each processor at the same time is selected at the scan circuit and written in a memory R in the order of scanning. A data processor D displays the information recorder in the memory R on a display device and stores it on a floppy disc. When a signal is transferred to the display device or the like in the order of recording, the relation of time such as mutual program execution state in processors 1a-1n can easily be grasped.
JP56030711A 1981-03-04 1981-03-04 Program executing state recording system in multiprocessor system Pending JPS57146353A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56030711A JPS57146353A (en) 1981-03-04 1981-03-04 Program executing state recording system in multiprocessor system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56030711A JPS57146353A (en) 1981-03-04 1981-03-04 Program executing state recording system in multiprocessor system

Publications (1)

Publication Number Publication Date
JPS57146353A true JPS57146353A (en) 1982-09-09

Family

ID=12311224

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56030711A Pending JPS57146353A (en) 1981-03-04 1981-03-04 Program executing state recording system in multiprocessor system

Country Status (1)

Country Link
JP (1) JPS57146353A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233875A (en) * 1986-04-04 1987-10-14 Hitachi Ltd Decentralized processing system and its method
DE19930120A1 (en) * 1999-06-30 2001-01-11 Siemens Ag Multiprocessor-trace concept for system-on-semiconductor chip applications

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320740A (en) * 1976-08-10 1978-02-25 Takeda Riken Ind Co Ltd Data input address control device
JPS5533288A (en) * 1978-08-31 1980-03-08 Fujitsu Ltd Hysteresis recording control system of multi-processor system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5320740A (en) * 1976-08-10 1978-02-25 Takeda Riken Ind Co Ltd Data input address control device
JPS5533288A (en) * 1978-08-31 1980-03-08 Fujitsu Ltd Hysteresis recording control system of multi-processor system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62233875A (en) * 1986-04-04 1987-10-14 Hitachi Ltd Decentralized processing system and its method
DE19930120A1 (en) * 1999-06-30 2001-01-11 Siemens Ag Multiprocessor-trace concept for system-on-semiconductor chip applications

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