JPS5489173A - Sequence controller - Google Patents

Sequence controller

Info

Publication number
JPS5489173A
JPS5489173A JP15701277A JP15701277A JPS5489173A JP S5489173 A JPS5489173 A JP S5489173A JP 15701277 A JP15701277 A JP 15701277A JP 15701277 A JP15701277 A JP 15701277A JP S5489173 A JPS5489173 A JP S5489173A
Authority
JP
Japan
Prior art keywords
data
exchange device
memory
data memory
flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15701277A
Other languages
Japanese (ja)
Other versions
JPS6027401B2 (en
Inventor
Toshihiko Yomogida
Takeshi Yokota
Katsumi Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyoda Koki KK
Original Assignee
Toyoda Koki KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyoda Koki KK filed Critical Toyoda Koki KK
Priority to JP15701277A priority Critical patent/JPS6027401B2/en
Publication of JPS5489173A publication Critical patent/JPS5489173A/en
Publication of JPS6027401B2 publication Critical patent/JPS6027401B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Control By Computers (AREA)
  • Programmable Controllers (AREA)

Abstract

PURPOSE: To exchange data without intermittent computing processing operation, by changing over a data memory effective for a computing processing portion and a data memory effective for a data exchange device at a fixed period.
CONSTITUTION: When the initial condition of input and output elements are written in to data memories 22, 23 and the reading of a sequence program is started, a flip-flop FF1 is inverted, a computing processor 30 can read and write in data to the data memory 22 and a data exchange device 24 to the data memory 23, and a signal from the memory 23 is transferred to input and output units 11, 12. When the sequence program is executed at a time, the flip-flop FF1 is again inverted, and the computing processor 30 and the data exchange device 24 are each connected to the memories 22, 23.
COPYRIGHT: (C)1979,JPO&Japio
JP15701277A 1977-12-26 1977-12-26 sequence controller Expired JPS6027401B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15701277A JPS6027401B2 (en) 1977-12-26 1977-12-26 sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15701277A JPS6027401B2 (en) 1977-12-26 1977-12-26 sequence controller

Publications (2)

Publication Number Publication Date
JPS5489173A true JPS5489173A (en) 1979-07-14
JPS6027401B2 JPS6027401B2 (en) 1985-06-28

Family

ID=15640240

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15701277A Expired JPS6027401B2 (en) 1977-12-26 1977-12-26 sequence controller

Country Status (1)

Country Link
JP (1) JPS6027401B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815203U (en) * 1981-07-16 1983-01-31 オムロン株式会社 programmable controller
JPS638804A (en) * 1986-06-27 1988-01-14 Koyo Denshi Kogyo Kk Programmable controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5815203U (en) * 1981-07-16 1983-01-31 オムロン株式会社 programmable controller
JPS6217847Y2 (en) * 1981-07-16 1987-05-08
JPS638804A (en) * 1986-06-27 1988-01-14 Koyo Denshi Kogyo Kk Programmable controller

Also Published As

Publication number Publication date
JPS6027401B2 (en) 1985-06-28

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