JPS6217847Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to a programmable controller, and particularly to a technique for increasing the execution processing speed of a user program.

As is well known, general programmable controllers such as ladder diagram type and logic symbol type basically have a user program memory that stores a sequence control program arbitrarily created by the user, and an external input signal. , an input circuit that sends an external output signal, an input/output memory that temporarily stores input/output data, etc. corresponding to the input circuit and output circuit, and the user program memory that sequentially executes each instruction at high speed. an instruction execution means for repeatedly reading and decoding the data, performing arithmetic processing based on the data in the input/output memory, and rewriting the data in the input/output memory with the results of the arithmetic processing; The input/output updating means writes data into a predetermined area of the memory and sets the output data of the predetermined area of the input/output memory to the output circuit.

The most important performance of this type of programmable controller is processing speed.

In a normal programmable controller, in addition to bit operations on input/output data and input/output update operations based on the user program described above, processing related to the program console, such as displaying the progress of operations and input/output status on a monitor, is performed. There is. It is necessary to make the processing cycle of the programmable controller, which includes all of these processing operations, as short as possible. As is well known, when this processing cycle becomes longer, the response delay between a change in the external input signal and the change in the external output based on that change increases, and small pulse-like changes in the external input signal occur. This causes various problems such as not being accepted by the controller.

The execution operation of one user instruction by the above-mentioned instruction execution means in a conventional programmable controller includes an instruction reading stage of updating the program counter and reading out the instruction to be executed from the user program memory, and decoding the read instruction. The system was divided into two stages: an instruction execution stage, and these stages were configured to be performed serially in time. Here, since the above-mentioned instruction execution stage mainly involves relatively simple bit operations, the processing time thereof is not so long. On the other hand, the above-mentioned instruction reading stage is influenced by the characteristics of the memory element used as the user program memory, and although access time has become considerably shorter in recent IC memories, the processing time of the instruction execution stage still remains. The processing time of this instruction reading stage is relatively large in the execution time of one instruction. As mentioned above, this has been highlighted as a major constraint in shortening the processing cycle of programmable controllers.

This idea was devised in view of the conventional problems mentioned above, and its purpose is to perform the instruction reading stage and the instruction execution stage in parallel, thereby significantly shortening the execution processing time of the user program. An object of the present invention is to provide a programmable controller that can perform the following functions.

In order to achieve the above object, the programmable controller of the present invention includes, as the instruction execution unit, a program counter for sequentially addressing the user program memory, and temporarily stores instructions read from the user program memory. and an instruction register, and at the same time or immediately after latching the instruction at address N read from the user program memory in the instruction register, the program counter is set to address N+1.
The operation of reading out the instruction at address N+1 from the user program memory is performed in parallel with the operation of decoding and executing the instruction at address N in the instruction register, and
The feature is that the CPU issues an STA signal to start the instruction execution section, receives an END signal from the instruction execution section, ends the operation of the instruction execution section, and simultaneously starts executing input/output update control. shall be.

Hereinafter, embodiments of this invention will be described in detail based on the drawings.

FIG. 1 is a block diagram showing the overall configuration of a programmable controller to which the present invention is applied. In this programmable controller, the CPU 1 executes the system program stored in the ROM 2, uses the RAM 3 as the system working memory, controls the entire programmable controller by timing control, the control as the input/output update means mentioned above, and the program console. 5, and the operation as the instruction execution means described above is performed by the instruction execution unit 6 in response to instructions from the CPU 1.

In the instruction execution cycle, the CPU 1 gives an operation command to the instruction execution section 6 by setting the start signal STA to "1". When the signal STA becomes "1", the instruction execution unit 6 starts executing the user program stored in the user program memory 7. At the same time, the signal STA becomes "1", so the multiplexer 11
connects the output of program counter 9 to the address line of user program memory 7, and multiplexer 12 connects the output of instruction register 10 to the address line of input/output memory 8. In addition, upon receiving the signal STA="1", the gate 13 connects each data input/output line of the user program memory 7 and the input/output memory 8 to the data bus DB on the CPU 1 side.
and 14 are turned off. That is, signal STA=
When it is "1", the user program memory 7 and input/output memory 8 are disconnected from the CPU 1 side,
It is connected to the instruction execution unit 6 side.

In the above state (STA="1"), the instruction execution unit 6 controls the program counter 9 and sequentially addresses the user program memory 7 from the first address based on the output of the program counter 9 to address the user program stored in the user program memory 7. The program is read into the instruction register 10 one instruction at a time.

FIG. 2 is a timing chart showing the relationship between the machine cycle of the instruction execution section 6 and the control of the program counter 9 and instruction register 10. In the figure, φ1 is the basic clock of the instruction execution unit 6,
φ2 is a clock whose frequency is divided by 1/2. The instruction execution unit 6 performs control operations with one cycle of φ2 as one machine cycle. Also, as shown in Figure 1,
The signal CK output from the instruction execution section 6 is applied as an increment signal to increment the program counter 9, and at the same time is applied as a latch signal to the instruction register 10 to latch the instruction read from the user program memory 7. It is becoming more and more common. This step/latch signal CK is output at the end of each machine cycle, as shown in FIG.
The program counter 9 is incremented in response to the fall of the signal CK. Also, the instruction register 10
performs a latch operation in response to the fall of the signal CK. Therefore, as shown in Figure 2, when the signal CK falls at the end of machine cycle #1,
In response to this, the program counter 9 is incremented,
Its output changes from N-1 to N. Of course, this change involves a certain amount of time delay. Further, the user program memory 7 is in the read mode during the instruction execution cycle, and as the output of the program counter 9 changes from N-1 to N, the instruction output from the user program memory 7 is also set to address N. -1 instruction changes to the next address N instruction. However, the time Td (access time) from when the signal CK falls at the end of machine cycle #1 until the command at address N is stably output to the data input/output terminal of the user program memory 7 is as described above. As shown in Fig. 2, it is not that small, but it occupies a very large proportion during the machine cycle, as shown in Fig. 2. On the other hand, in response to the fall of the signal CK at the end of machine cycle #1, the instruction register 10 performs a latching operation, but what is latched in the instruction register 10 at this time is not the instruction at address N, but the user's instruction. This is the command at address N-1 before the data output of the program memory 7 changes. Naturally, there is a response delay in the latch operation of the instruction register 10, but it is extremely small, and as shown in FIG. The time ΔT until N-1 instructions are latched is very small. That is, when the machine cycle changes from #1 to #2, the instruction at address N-1 is latched in the instruction register 10 in a very short time, and this instruction is decoded and executed in machine cycle #2. That is, the input/output address of the instruction latched in the instruction register 10 addresses the input/output memory 8 via the multiplexer 12, and the instruction code is supplied to the instruction execution unit 6 and decoded. Then, the instruction execution unit 6 performs a logical operation on the previous logical operation result and the input/output data read from the input/output memory 8 according to the instruction code, and further writes the result to the input/output memory 8. It performs the following operations. This operation is performed in machine sile #2.

Then, at the end of machine cycle #2, the signal CK
falls, the program counter 9 is incremented, and the instruction register 10 performs a latch operation. At this time, the instruction at address N is latched in the instruction register 10, and this instruction is decoded and executed during the next machine cycle #3. Also, the program counter 9 is incremented to N+1, and the user program memory 7 is now addressed, and from the user program memory 7 the time Td is incremented.
The instruction at address N+1 is read out after a delay of . That is, in machine cycle #3, the decoding and execution of the instruction at address N and the reading stage of the instruction at address N+1 are performed in parallel.
Therefore, compared to the conventional method where the instruction reading stage and the instruction execution stage were performed serially in time,
The instruction execution processing time is significantly reduced.

Note that when the instruction execution unit 6 finishes executing up to the last instruction in the user program memory 7, it issues an end signal.
Set ENT to "1" to notify CPU 1 of the end of one round of execution of the user program. In response to this, the CPU 1 returns the start signal STA to "0", switches the multiplexers 11 and 12, turns on the gates 13 and 14, and closes the user program memory 7 and input/output memory 8.
Connect to address bus AB and data bus DB of CPU1. First, an input/output update operation is performed in which the output data of the input/output memory 8 is transmitted to the output circuit of the input/output section 4, and the input data of the input circuit of the input/output section 4 is stored in a predetermined area of the input/output memory 8. Execute. In addition, it also controls monitor processing related to the program console after the console. After performing these series of controls, the CPU 1 sets the start signal STA to "1" again.
Then, the instruction execution unit 6 starts executing the user program as described above.

As explained in detail above, in the programmable controller according to this invention, the instruction reading stage and the instruction execution stage of the user program are performed in parallel, so the access time of the user program memory affects the processing speed of the user program. , and the overall processing speed can be significantly improved.

Further, according to this invention, while achieving a high processing speed, the instruction execution section itself can be constructed from a relatively simple bit operation circuit, so that there is an advantage that no particular increase in cost occurs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a programmable controller to which the present invention is applied, and FIG. 2 is a timing chart showing an instruction execution operation of the programmable controller. 6... Instruction execution unit, 7... User program memory, 8... Input/output memory, 9... Program counter, 10... Instruction register.

Claims (1)

[Claims for Utility Model Registration] A user program memory that stores a sequence control program arbitrarily created by the user, an input circuit to which an external input signal is given, an output circuit to send an external output signal, and the above input. An input/output memory that temporarily stores input/output data, etc. corresponding to the circuit and output circuit, and each instruction in the user program memory is sequentially and repeatedly read out at high speed, decoded and executed, and arithmetic processing is performed based on the data in the input/output memory. With,
an instruction execution unit that rewrites data in the input/output memory with the result of the arithmetic processing; and an instruction execution unit that writes the input data of the input circuit to a predetermined area of the input/output memory, and writes the output data of the predetermined area of the input/output memory to the A programmable controller having: a CPU that executes input/output update processing to be set in an output circuit; and a program counter for sequentially addressing the user program memory; and a program counter for sequentially addressing the user program memory; and an instruction register for temporarily storing instructions read from the user program memory, and at the same time or immediately after latching the instruction at address N read from the user program memory in the instruction register, the program counter is incremented to address N+1, The CPU is configured such that the operation of reading the instruction at address N+1 from the memory is performed in parallel with the operation of decoding and executing the instruction at address N in the instruction register, and the CPU issues an STA signal to start the instruction execution unit. A programmable controller characterized in that the programmable controller is configured to receive an END command from the instruction execution section, terminate the operation of the instruction execution section, and simultaneously execute input/output update control.