JPH0638209B2 - Programmable controller - Google Patents

Description

The present invention relates to a programmable controller, and more specifically, proposes a programmable controller capable of increasing the response speed of output information with respect to input information.

FIG. 1 is a block diagram schematically showing the configuration of a known general programmable controller (hereinafter referred to as controller), which is an external input device 8 such as a switch or a relay contact.
Input section 6 for capturing and storing the state of
The information stored in the program memory 2 is read and the calculation unit 1 for executing the calculation according to the control command stored in advance in the program memory 2, the program memory 2 and the program counter 3 as the address counter thereof, and the calculation result of the calculation unit 1 are temporarily stored. The intermediate information storage unit 4 and the output information unit 5 for converting the content of the calculation result output of the calculation unit 1 into a required voltage level and outputting it to an external output device 7 such as a relay coil or an actuator. ing.

Thus, the input information section 6 causes inconvenience if the content of the input information is changed during execution of the operation. Therefore, the state of the front input device 8 is read before the sequential execution of the control commands in the program memory 2. It works to latch information in this state,
This is intended to eliminate the inconvenience.

FIG. 2 shows the reading of the input information and the execution of the control command following the input information by setting the time axis up and down. 1 from the start of reading the input information to the execution of the final control instruction at address n
This is called scan time, and the operation during this time is repeatedly executed. The above-mentioned 1 scan time is generally several tens of ms,
This appears as a response delay between the input information and the output information that should reflect it.

FIG. 3 is a ladder diagram showing the circuit to be controlled. In the circuit Q, the coil of the relay Y is excited through the normally closed contact B in the closed circuit of the normally open contact A, and the relay Y is normally opened. The contents are such that the self-holding is performed by closing the contact and the self-holding is released by opening the contact B, and the contents of the circuit P before and after that are at addresses 0 to m−1 of the program memory 2, It is also assumed that the contents of the circuit Q are stored in the addresses m to m + 3 and the contents of the circuit R in the subsequent stage are stored in the addresses m + 4 to n. Now, the response time from the opening of the contact B to the release of the self-holding when the relay Y is self-holding will be described. For convenience of explanation, assume that 1 scan time is 50 ms, input information is 1 ms, control command execution time is 49 ms, and the time until the control command for circuit Q is executed is 40 m.
Let s.

Since the input information is read in the first 1 ms of the scan time, the state change after that is not given to the arithmetic unit 1 until the next scan time. For example, 20 m after starting reading the input information
If contact B is opened at the time of s, this state is 30
Input at the time of reading the next input information after ms, then 40 m
Self hold release will be performed after s, total 70 m
This will cause a delay in the response of s. Although most of the operations of the device have a response speed of several tens of ms corresponding to one scan time, there is no problem, but for a special device, a higher speed response may be desired. When the operation time of the input device is shorter than the scan time, for example, the contact B is 10 ms.
When the circuit is opened to some extent, there is a problem that the state cannot be read and self-holding cannot be released.

As a solution to the problem of improving response speed, Japanese Examined Patent Publication 54-1
Although there is one disclosed in Japanese Patent No. 58588, when the open circuit is detected, the control based on the detection result cannot be performed when the open circuit is short.

The present invention has been made in view of such circumstances, and for some devices, whether or not the input information is changed is monitored at a predetermined timing during execution of a control command, and if it is changed, It is an object of the present invention to provide a controller capable of immediately executing a control command related to the input information to speed up the response speed.

The present invention will be specifically described below with reference to the drawings.

FIG. 4 is a block diagram schematically showing the configuration of the controller according to the present invention. An arithmetic unit 1 composed of a microprocessor for decoding data transfer control input information and executing control instructions, a program memory 2 for storing control instructions,
The state of the program counter 3 as the address counter, the intermediate information storage unit 4 for temporarily storing the output information, the output information unit 5 as the interface for the external output device 7, and the external input device 8 are stored and stored. However, the hardware configuration of the input information section for causing the arithmetic section 1 to read this is exactly the same as the conventional one shown in FIG. In addition to these components, the device of the present invention is provided with an input circuit 9 and a register 10. The input circuit 9 is a circuit for converting an operating state of an external device such as an external relay contact or a switch into an electric signal suitable for reading into the arithmetic unit 1, and has a number equal to or less than that of the input information unit 6. The input device 8 is provided with a connection terminal, and an input device that needs to improve responsiveness, for example, the contact B is also connected to the input circuit 9. The input circuit 9 can be shared by a part of the input information section 6. That is, it is sufficient to use a part up to the conversion of the input information from the input device 8 into an electric signal suitable for reading into the calculation part 1, and to provide a branch output at this part.

The arithmetic unit 1 reads the stored contents of the input information unit 6 while the input information reading process is being executed.
When executing, the designated output of the input circuit 9 is read.

The register 10 is for saving the data contents of the program counter 3, and when the arithmetic unit 1 executes the control instruction IN, the contents of the program counter 3 are stored in the register 10.
And the data content of the program counter 3 is set to the head address of a predetermined range of the program memory 2. Further, when the arithmetic unit 1 executes a control command RST 0 described later, the data content of the register 10 is set back to the program counter 3. The register 10 may be in the arithmetic unit 1.

FIG. 5 shows the control instructions stored in the program memory 2 as in FIG. It is assumed that the circuit that needs to increase the response speed is the circuit Q in FIG. This circuit Q
The control command relating to (i) may be stored in any part (it may be from the address m as shown in FIG. 2).
It shall be stored at the address. Then, after this control instruction, that is, the reset instruction RST 0 is written at the address 4. In this way, when the control command for the circuit Q is written in the addresses 0 to 4, the above-mentioned start address becomes the address 0.

The control command relating to the circuits P and R is stored in the other address of the program memory 2, but the state of the contact B is read according to the necessity of the response speed from the opening operation of the contact B to the demagnetization of the relay coil Y. Write the compulsory shift command IN B (however, B is actually the number assigned to the contact B) at the required number and frequency.

Next, the processing of the arithmetic unit 1 when the forced transfer instruction INB is read will be explained based on the flow chart of FIG.
First, the state of the corresponding input device, that is, the contact B is read via the input circuit 9. Contact B newly read via input circuit 9
The state of is stored in the register in the arithmetic unit 1 described above. This may be stored in RAM (random access memory). Then, the content is compared with the content at the time of the previous execution of the control command, that is, the content previously read from the input circuit 9 and stored, and if they match, the content of the program counter 3 is incremented by 1 with the contact B being unchanged. Read the next control command. On the other hand, if they do not match, it is determined that the contact B has changed and the contents of the program counter 3 (for example, m, n, p in the case of FIG. 5) are saved and stored in the register 10, and the program counter 3 has a circuit Q. The start address 0 of the range in which the control command relating to is stored is set. Therefore 0, 1,
The control command at addresses 2 and 3 is forcibly executed, and when the contact B opens, the coil of the relay Y is immediately demagnetized. When executing this instruction, the information on the state of the contact B already stored in the register or the like is used.
In the example of FIG. 5, there is no change at the address m, but there is a change between the addresses m and n, and this is detected at the address n and returned to the address 0 by a solid arrow.

Next, a reset command RST 0 based on the flowchart of FIG.
The process when is read will be described. When the instructions of addresses 0 to 3 are executed as described above, the instruction of address 4, that is, the reset instruction RST 0 is read next. Then, the arithmetic unit 1 restores and sets the data content of the register 10 to the program counter 3, and then increments the content of the program counter 3 by one. As a result, for example, n + 1
The instruction at the address, that is, the instruction following the compulsory shift instruction INB, is returned to the execution state. In the example of FIG. 5, the dashed arrow indicates that the instruction at address n + 1 is executed following address 4.

As described above, not only is the state of the input device 8 latched therein read from the input information section 6, but the required state of the input device is passed via the input circuit 9 once or more during the execution of the control command in one scan time. It is decided to read without delay, and if this read data is different from the previously read data, it is immediately forcibly transferred to the execution of the control command related to the change, so that it is controlled by the input device and this. The response between the output devices is significantly speeded up. Now compulsory shift command IN
If B is written at 10 ms intervals, and if it takes 1 ms to execute the instructions at addresses 0 to 3, the self-holding of relay Y will be released in 11 ms even under the worst conditions. Become. Needless to say, the shorter the time interval, the higher the responsiveness. In addition, the compulsory shift command INB
Of course, it is possible to write for multiple input devices. In the case of an instruction that is forcibly transferred and executed, the same input device status that was used to determine this transfer is read from the register or RAM and used, so changes in the input device status during execution of this instruction are taken into consideration. No need.
Therefore, the time width of the signal indicating the state of the input device is
The interval of is sufficient, and it is effective in increasing the response speed.

As described above, the programmable controller according to the present invention includes a program memory for storing a control instruction, a program counter for designating a read address of the program memory, an arithmetic unit for performing an arithmetic operation according to the control instruction read from the program memory, In a pluggable controller having an input information section for periodically updating and storing input information from an external apparatus and giving the stored information to a computing section to store the information, the input information from the external apparatus is passed through the input information section. An input circuit that can be given to an arithmetic unit to store the data, and a register that saves the data content of the program counter, and arithmetically operates input information from an external device specified in the control instruction through the input circuit. And store the input information in the external device via the input circuit. The means for comparing with the input information stored therein and the data contents of the program counter are saved in the register when the comparison result does not match, and the start address of the predetermined range of the program memory is set in the program counter to set the predetermined range. Means for forcibly shifting to the execution of the control instruction of (1), and means for setting the data contents saved in the register in the program counter after the execution of the control instruction of the predetermined range, the input circuit when executing the control instruction of the predetermined range. It is characterized in that it uses input information from an external device which is given to and stored in a calculation unit via a high-speed response speed for a specific device such as a safety device to a desired speed. Can be converted. Further, the response speed can be freely set by changing the program, which is highly convenient. In addition, even if a device that operates instantaneously is incorporated as an external device, it does not fail to detect the operation, and it is possible to perform arithmetic control by following the detection result.
The present invention has excellent effects.

[Brief description of drawings]

1 is a schematic block diagram of a general controller, 2
FIG. 3 is an explanatory diagram of the operation of the arithmetic unit, FIG. 3 is a ladder circuit diagram, FIG. 4 is a schematic block diagram of the controller of the present invention, and FIG.
FIG. 6 and FIG. 7 are flow charts showing the execution contents of the instruction. 1 ... Calculation unit, 2 ... Program memory, 3 ... Program counter, 6 ... Input information unit, 9 ... Input circuit, 1
0 ... Register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-54-158588 (JP, A) JP-A-51-41189 (JP, A) JP-A-53-5385 (JP, A) JP-A-56- 140407 (JP, A) JP 56-145402 (JP, A) JP 57-39408 (JP, A)

Claims (1)

[Claims] 1. A program memory for storing a control instruction, a program counter for designating a read address of the program memory, an arithmetic unit for performing an arithmetic operation according to the control instruction read from the program memory, and input information from an external device. In a programmable controller having an input information section for periodically updating and storing and giving stored information to an arithmetic section, the input information from an external device is given to the arithmetic section and stored without passing through the input information section. An input circuit for obtaining the data content of the program counter, and a register for saving the data content of the program counter, and input information from an external device designated in the control instruction is given to the arithmetic unit via the input circuit to be stored therein. Means for comparing the input information with the input information already provided from the external device via the input circuit, When the result does not match, the data content of the program counter is saved in the register, while the start address of a predetermined range of the program memory is set in the program counter and the control instruction in the predetermined range is forcibly transferred to the register. Means for setting the data content saved in the register to the program counter after executing the control instruction in the predetermined range, and when the control instruction in the predetermined range is executed, it is given to the arithmetic unit via the input circuit and stored therein. A programmable controller characterized in that input information from a device is used.