JPH03204031A - System for suppressing execution of program - Google Patents

Abstract

PURPOSE:To shorten the processing time in the suppressing system by applying a return address of a subroutine to a fetch address of the next instruction of a CPU with the detection output when the address of a subroutine jumping instruction is detected. CONSTITUTION:A CPU 1 executes a subroutine jumping instruction to a program address where the selection output is obtained via an address selection circuit 7. Under such conditions, no signal is applied to a selector 3 as long as a switch 6 is turned off and an AND gate 2 is closed. Then the processing is carried out with a jump given to the subroutine. When the switch 6 is turned on and the gate 2 is opened, a control signal is applied to the selector 3 and the fixed data is given to the CPU 1 from a fixed data circuit 5. Since this fixed data is set to a return address of the subroutine, the due subroutine is not processed and the processing of only a main program is carried on.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program execution inhibiting method, and particularly to a program execution inhibiting method in which a specific subroutine program provided in a main program is not executed according to an instruction.

[Conventional technology]

2. Description of the Related Art As a maintenance function in an information processing apparatus, when it is desired to collect the execution history of a main program, there is a function that executes an execution history collection program provided as a subroutine in a part of the main program. However, this execution history collection program often inhibits execution during normal processing in order to shorten processing time. Conventionally, to prevent this, the main program has a visible switch whose value can be changed by instructions from a host device or other operation panel, and the central processing unit reads the value of this switch and either suppresses or executes the action. The system uses an execution suppression method that determines whether or not to proceed.

[Problem to be solved by the invention]

The conventional program execution suppression method described above requires at least three instructions, such as reading, determining, or returning the value of a visible switch, and is difficult to use when it is frequently determined whether to suppress program execution. The disadvantage of this method is that the processing for determining whether to suppress it requires a large amount of overhead.

[Means to solve the problem]

The program execution suppression method of the present invention suppresses execution of a specific subroutine program provided in a main program in response to an external instruction in an information processing apparatus.
a switching means for holding the instruction from the outside; an address selection circuit for detecting the address of a subroutine jump instruction to the specific subroutine program; a fixed storage circuit for holding the return address of the specific subroutine program; a selector that selects data from either the memory circuit to be stored or the fixed storage circuit and supplies the selected data to the central processing unit; and a detection signal from the address selection circuit that is controlled by the output of the switching means and input to the control input of the selector. and gate means for providing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, in which a data bus 8 is connected to a central processing unit (hereinafter referred to as CPU) 1,
A selector 3 is connected to the data bus 8, and two other data buses are connected to the selector 3, one of which is the data bus 9.
A memory circuit 4 for storing a program is connected to one bus, and a fixed storage circuit 5 for outputting fixed data set in advance is connected to the other data bus. On the other hand, the output line of the address selection circuit 7 connected to the address bus from the CPU and the output line of the switch 6 connected to the power supply Vcc are input to the AND gate 2, and the output line of the AND gate 2 is input to the selector 3.
This is the control line.

Assume that in the above configuration, the CPUI executes a subroutine jump instruction to a program address from which a selected output is obtained by the address selection circuit 7.

At this time, switch 6 is off and AND gate 2
If the selector 3 is closed, no control signal is given to the selector 3, and the CPU jumps to a subroutine to perform processing regardless of the above selection output. Next, switch 6
is on and the AND gate 2 is open, a control signal is given to the selector 3, and fixed data from the fixed data circuit 5 is given to the CPUI. Since this fixed data is set at the return address of the subroutine, the subroutine that is about to be executed will not be processed, and only the main program will be processed. That is, by turning on switch 6, execution of the subroutine is inhibited.

In the above embodiment, the switch 6 was operated directly by hand, but even if it is operated by a command from a host device, it will not be turned off at all. Further, the address selection circuit 7 is designed to select the address of the subroutine jump instruction, but if the address of the subroutine jump instruction is determined by the logical value of a specific address line, this address line may be input directly to the AND gate 2. It doesn't scoop at all.

〔Effect of the invention〕

As explained above, in the present invention, when the address of a subroutine jump instruction is detected, if an instruction to suppress execution of the subroutine has been given, this detection output allows
By having means for giving the return address of the subroutine to the fetch address of the next instruction of the central processing unit, program execution can be inhibited without reading data for switching and determining whether switching is possible, thereby reducing processing time. This has the effect of shortening the time.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention.

Claims (1)

[Claims] In an information processing device that suppresses execution of a specific subroutine program provided in a main program based on an external instruction, switching means for retaining the external instruction and an address of a subroutine jump instruction to the specific subroutine program are provided. an address selection circuit that detects the return address of the specific subroutine program, a fixed memory circuit that holds the return address of the specific subroutine program, a memory circuit that stores the program, and data from either of the fixed memory circuit and the selected data and provides the selected data to the central processing unit. A program execution inhibiting method comprising: a selector; and gate means for controlling a detection signal from the address selection circuit by the output of the switching means and applying it to a control input of the selector.