JPS5815203U - programmable controller - Google Patents

programmable controller

Info

Publication number
JPS5815203U
JPS5815203U JP10559481U JP10559481U JPS5815203U JP S5815203 U JPS5815203 U JP S5815203U JP 10559481 U JP10559481 U JP 10559481U JP 10559481 U JP10559481 U JP 10559481U JP S5815203 U JPS5815203 U JP S5815203U
Authority
JP
Japan
Prior art keywords
input
output
instruction
memory
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10559481U
Other languages
Japanese (ja)
Other versions
JPS6217847Y2 (en
Inventor
松浦　利美
Original Assignee
オムロン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by オムロン株式会社 filed Critical オムロン株式会社
Priority to JP10559481U priority Critical patent/JPS5815203U/en
Publication of JPS5815203U publication Critical patent/JPS5815203U/en
Application granted granted Critical
Publication of JPS6217847Y2 publication Critical patent/JPS6217847Y2/ja
Granted legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案を適用したプログラマブル・コントロー
ラの一実施例を示すブ爾ツク図、第２図は同上プログラ
マブル拳コントローラの命令実行動作を示すタイミング
チャートである。 ６・・・・・・命冷実行部、７・・・・・・ユーザプロ
グラムメモリ、８・・・・・・入出カメモリ、９・・・
・・・プログラムカウンタ、１０・・・・・・命令レジ
スタ。FIG. 1 is a block diagram showing an embodiment of the programmable controller to which the present invention is applied, and FIG. 2 is a timing chart showing the command execution operation of the programmable fist controller. 6... Life cold execution unit, 7... User program memory, 8... Input/output memory, 9...
...Program counter, 10...Instruction register.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 使用者側にて任意に作成されたシーケンス制御プログラ
ムを格納するユーザプログラムメモリと、外部入力信号
が与えられる入力回路と、外部出力信号を送出する出力
回路と、上記入力回路および出力回路に対応した入出力
データ等を一時記憶する入出カメモリと、上記ユーザプ
ログラムメモリの各命令を順次高速に繰り返し読出して
解読実行し、上記入出カメモリのデータに基づいて演算
処理するとともに、その演算処理結果で上記入出カメモ
リのデータを書換える命令実行手段と、上記入力回路の
入力データを上記入出カモメ′すの所定エリアに書込む
とともに、上記入出カメモリの所定エリアの出力データ
を上記出力回路にセットする入出力更新手段とを有する
プログラマブル・コントローラにおいて、上記命令実行
手段は、上記ユーザプログラムメモリを順番にアドレッ
シングするためのプログラムカウンタと、上記ユーザプ
ログラムメモリから読出された命令を一時記憶する命令
レジスタとを有し、この命令レジスタに上記ユーザプロ
グラムメモリから読出されたアドレスＮの命令をラッチ
すると同時あるいは直後に上記プログラムカウンタをア
ドレス（Ｎ＋ｌ）に歩進させ、上記ユニザブログラムメ
モリからアドレス（Ｎ＋１）の命令を読出す動作が、上
記命令レジスタ中のアドレスＮの命令の解読実行動作と
並列的に行われるように構成したことを特徴とするプロ
ゲラマフ゛ル拳コントローラ。A user program memory that stores a sequence control program arbitrarily created by the user, an input circuit to which an external input signal is applied, an output circuit to send an external output signal, and a circuit corresponding to the above input circuit and output circuit. The input/output memory temporarily stores input/output data, etc., and each instruction in the user program memory is sequentially and repeatedly read out at high speed, decoded and executed, and arithmetic processing is performed based on the data in the input/output memory. a command execution means for rewriting data in the input/output memory; and writing input data of the input circuit into a predetermined area of the input/output gull, and setting output data of the predetermined area of the input/output memory into the output circuit. In the programmable controller, the instruction execution means includes a program counter for sequentially addressing the user program memory, and an instruction register for temporarily storing instructions read from the user program memory. At the same time or immediately after latching the instruction at address N read from the user program memory in this instruction register, the program counter is incremented to address (N+l), and the instruction at address (N+1) is read from the uniprogram memory. 2.) A programmer full fist controller characterized in that the operation of reading out the instruction at address N in the instruction register is performed in parallel with the operation of decoding and executing the instruction at address N in the instruction register.
JP10559481U 1981-07-16 1981-07-16 programmable controller Granted JPS5815203U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10559481U JPS5815203U (en) 1981-07-16 1981-07-16 programmable controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10559481U JPS5815203U (en) 1981-07-16 1981-07-16 programmable controller

Publications (2)

Publication Number Publication Date
JPS5815203U true JPS5815203U (en) 1983-01-31
JPS6217847Y2 JPS6217847Y2 (en) 1987-05-08

Family

ID=29900124

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10559481U Granted JPS5815203U (en) 1981-07-16 1981-07-16 programmable controller

Country Status (1)

Country Link
JP (1) JPS5815203U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61195458A (en) * 1985-02-25 1986-08-29 Fujitsu Ltd Telegram transmission and reception control method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489173A (en) * 1977-12-26 1979-07-14 Toyoda Mach Works Ltd Sequence controller
JPS5611504A (en) * 1979-07-11 1981-02-04 Japan Atom Energy Res Inst Control timing system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489173A (en) * 1977-12-26 1979-07-14 Toyoda Mach Works Ltd Sequence controller
JPS5611504A (en) * 1979-07-11 1981-02-04 Japan Atom Energy Res Inst Control timing system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61195458A (en) * 1985-02-25 1986-08-29 Fujitsu Ltd Telegram transmission and reception control method

Also Published As

Publication number Publication date
JPS6217847Y2 (en) 1987-05-08

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