JPS62109249U - - Google Patents
Info
- Publication number
- JPS62109249U JPS62109249U JP20143485U JP20143485U JPS62109249U JP S62109249 U JPS62109249 U JP S62109249U JP 20143485 U JP20143485 U JP 20143485U JP 20143485 U JP20143485 U JP 20143485U JP S62109249 U JPS62109249 U JP S62109249U
- Authority
- JP
- Japan
- Prior art keywords
- processor
- data
- output
- instructions
- storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Image Input (AREA)
Description
第１図は、本考案の一実施例を示す回路ブロツ
ク図、第２図は、第１図の装置におけるプロセツ
サ１１のメモリへのデータ書き込み命令の実行時
の各部の動作を示すタイミングチヤート、第３図
はメモリ空間を示す図、第４図は、第１図の装置
におけるプロセツサ１１の出力命令の実行時の各
部の動作を示すタイミングチヤート、第５図は、
ＩＯ空間を示す図である。
主要部分の符号の説明、１１……プロセツサ、
１４，１５……デコード回路、２０……Ｄ形フリ
ツプフロツプ、Ｇ１〜Ｇ９……ゲート。
FIG. 1 is a circuit block diagram showing an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of each part when the processor 11 in the device shown in FIG. 1 executes an instruction to write data to the memory. 3 is a diagram showing the memory space, FIG. 4 is a timing chart showing the operation of each part during execution of an output instruction from the processor 11 in the device shown in FIG. 1, and FIG.
It is a diagram showing IO space. Explanation of symbols of main parts, 11...Processor,
14, 15...decoding circuit, 20...D flip-flop, G1 to G9 ...gate.
Claims (1)
いる記憶位置へのデータの書き込みを指令するメ
モリ命令及び指定した入出力アドレスが予め割り
当てられている出力ポートへのデータの送出を指
令する出力命令を含む一連の命令群からなるプロ
グラムの各命令を順次実行するプロセツサによつ
て情報の処理を行なう情報処理装置であつて、所
定入出力アドレスが予め割り当てられた出力ポー
トへのデータ送出及び所定メモリアドレスが予め
割り当てられた記憶位置へのデータ書込みのうち
のいずれかを前記プロセツサが行なつたとき前記
プロセツサのデータパス上のデータを記憶保持す
る記憶手段を備え、前記記憶手段の記憶内容に応
じた制御信号を出力することを特徴とする情報処
理装置。 A series of memory instructions that direct data to be written to a storage location that has been previously assigned a specified memory address, and output instructions that commands that data be sent to an output port that has previously been assigned a specified input/output address. An information processing device that processes information using a processor that sequentially executes each instruction of a program consisting of a group of instructions, and that transmits data to an output port to which a predetermined input/output address is preassigned and a predetermined memory address is preassigned. The processor further comprises a storage means for storing and holding data on a data path of the processor when the processor writes data to any of the storage locations stored in the processor, and outputs a control signal according to the storage contents of the storage means. An information processing device characterized by outputting information.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20143485U JPS62109249U (en) | 1985-12-25 | 1985-12-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20143485U JPS62109249U (en) | 1985-12-25 | 1985-12-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62109249U true JPS62109249U (en) | 1987-07-11 |
Family
ID=31164881
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20143485U Pending JPS62109249U (en) | 1985-12-25 | 1985-12-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62109249U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5377148A (en) * | 1976-12-20 | 1978-07-08 | Matsushita Electric Ind Co Ltd | Input and output control circuit |
| JPS5644922A (en) * | 1979-09-20 | 1981-04-24 | Toshiba Corp | Input/output port designation system |
-
1985
- 1985-12-25 JP JP20143485U patent/JPS62109249U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5377148A (en) * | 1976-12-20 | 1978-07-08 | Matsushita Electric Ind Co Ltd | Input and output control circuit |
| JPS5644922A (en) * | 1979-09-20 | 1981-04-24 | Toshiba Corp | Input/output port designation system |
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