JPS5644922A - Input/output port designation system - Google Patents

Input/output port designation system

Info

Publication number
JPS5644922A
JPS5644922A JP12120079A JP12120079A JPS5644922A JP S5644922 A JPS5644922 A JP S5644922A JP 12120079 A JP12120079 A JP 12120079A JP 12120079 A JP12120079 A JP 12120079A JP S5644922 A JPS5644922 A JP S5644922A
Authority
JP
Japan
Prior art keywords
signal lines
access instruction
instruction
port
memory access
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12120079A
Other languages
Japanese (ja)
Inventor
Takatoshi Ishii
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP12120079A priority Critical patent/JPS5644922A/en
Publication of JPS5644922A publication Critical patent/JPS5644922A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To mekt it possible to execute the memory access instruction to facilitate designation of I/O ports, by making it possible to designate I/O ports by the I/O instruction as well as the memory access instruction.
CONSTITUTION: In case that the processor executes the I/O port instruction, signal lines AD6 and AD7 are turned on and the IO access instruction is transmitted to the IO-AC port. Then, AND6b and OR6c are turned on, and decoder 6a activates IO control 7 according to address signals of signal lines AD3WAD5 and selects registers 7a... by signal lines AD0WAD2. The IO device is driven according to control signal line R/W. In case of the memory access instruction, the RAM and the ROM are selected for 1 of signal lines AD14WAD15 and 1 of AD12WAD13 respectively. Consequently, the address code of upper 8 bits and the address code of lower 8 bits expressing the port number become the port number memory address stored in the memory mapped I/O area.
COPYRIGHT: (C)1981,JPO&Japio
JP12120079A 1979-09-20 1979-09-20 Input/output port designation system Pending JPS5644922A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12120079A JPS5644922A (en) 1979-09-20 1979-09-20 Input/output port designation system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12120079A JPS5644922A (en) 1979-09-20 1979-09-20 Input/output port designation system

Publications (1)

Publication Number Publication Date
JPS5644922A true JPS5644922A (en) 1981-04-24

Family

ID=14805336

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12120079A Pending JPS5644922A (en) 1979-09-20 1979-09-20 Input/output port designation system

Country Status (1)

Country Link
JP (1) JPS5644922A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109249U (en) * 1985-12-25 1987-07-11
JPS63211052A (en) * 1987-02-27 1988-09-01 Hitachi Ltd Io adapter

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62109249U (en) * 1985-12-25 1987-07-11
JPS63211052A (en) * 1987-02-27 1988-09-01 Hitachi Ltd Io adapter
JPH0575139B2 (en) * 1987-02-27 1993-10-19 Hitachi Ltd

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