JPS5552163A - Memory extension system - Google Patents

Memory extension system

Info

Publication number
JPS5552163A
JPS5552163A JP12343978A JP12343978A JPS5552163A JP S5552163 A JPS5552163 A JP S5552163A JP 12343978 A JP12343978 A JP 12343978A JP 12343978 A JP12343978 A JP 12343978A JP S5552163 A JPS5552163 A JP S5552163A
Authority
JP
Japan
Prior art keywords
data
memory
given
ram
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12343978A
Other languages
Japanese (ja)
Inventor
Toshihiko Ohori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP12343978A priority Critical patent/JPS5552163A/en
Publication of JPS5552163A publication Critical patent/JPS5552163A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To easily extend the memory, by selecting the upper rank memory with the value of memory designation register and address data from CPU, and selecting the lower rank memory with the address data only of CPU independently of the memory designation register.
CONSTITUTION: The lower rank RAM2 and upper rank RAM group 3 are provided for CPU1, they are connected via the address bus 4 and data bus 5, the address data A1WA14 are given to RAM2 and RAM group 3, A0 is given only to RAM2 and further, the readout and write-in instructions R/W are given to RAM's 2 and 3. Further, A1WA14 are inputted to the decoder 7, and the output is fed to the RAM designation register 8 when the readout and write-in instructions IR/W to the input and output unit I/O are given, and the designation data is set and it is fed to the gate circuit 10. Further, CPU1 is connected to the DMA controller 13 consisting of DMA control circuit 14, DMA address counter 15 and data conversion circuit 16, and data giving and receiving is made with the line 17.
COPYRIGHT: (C)1980,JPO&Japio
JP12343978A 1978-10-06 1978-10-06 Memory extension system Pending JPS5552163A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12343978A JPS5552163A (en) 1978-10-06 1978-10-06 Memory extension system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12343978A JPS5552163A (en) 1978-10-06 1978-10-06 Memory extension system

Publications (1)

Publication Number Publication Date
JPS5552163A true JPS5552163A (en) 1980-04-16

Family

ID=14860608

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12343978A Pending JPS5552163A (en) 1978-10-06 1978-10-06 Memory extension system

Country Status (1)

Country Link
JP (1) JPS5552163A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722281A (en) * 1980-07-16 1982-02-05 Hitachi Ltd Display unit extended in address space
JPS58501061A (en) * 1981-06-29 1983-06-30 松下電器産業株式会社 Computer with extended address function

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112547A (en) * 1973-02-06 1974-10-26

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49112547A (en) * 1973-02-06 1974-10-26

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5722281A (en) * 1980-07-16 1982-02-05 Hitachi Ltd Display unit extended in address space
JPS58501061A (en) * 1981-06-29 1983-06-30 松下電器産業株式会社 Computer with extended address function

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