JPS59134803U - Sequence control device - Google Patents
Sequence control deviceInfo
- Publication number
- JPS59134803U JPS59134803U JP2525983U JP2525983U JPS59134803U JP S59134803 U JPS59134803 U JP S59134803U JP 2525983 U JP2525983 U JP 2525983U JP 2525983 U JP2525983 U JP 2525983U JP S59134803 U JPS59134803 U JP S59134803U
- Authority
- JP
- Japan
- Prior art keywords
- control device
- sequence control
- sequence
- bit
- processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Programmable Controllers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はこの考案の一実施例であるシーケンス制御装置
の回路構成を示すプロ゛イク図、第２図は第１図のシー
ケンス演算回路内の回路構成を示す゛ブロック図、第３
図は第１図のシーケンス制御装置に適用されるＭＯＶ命
令を示す構成図である。
図において、１・・・中央処理装置（ＣＰＬＪ）、２・
・・クロックジェネレータ、３・・・バスコントローラ
、４・・・アドレスラッチ、５・・・アドレスデコーダ
、６・・・ｌ１０（入出力）インタフェース、７・・・
メモリ、訃・・シーケンス演算回路、９．１０・・・相
方向性バッファ、１１・・・命令デコーダ、１２・・・
演算器、１３・・・演算結果保持レジスタ、１４・・・
ＡＮＢ・ＯＲＢスタック、１５・・・マスクコントロー
ラ、１６・・・演算データ選択マルチプレクサ、１７・
・・データ保持レジスタ、１８・・・データスワップマ
ルチプレクサ、１９・・・タイミングジェネレータであ
る。なお、図中、同一符号は同一、又は相当部分を示す
。FIG. 1 is a block diagram showing the circuit configuration of a sequence control device that is an embodiment of this invention, FIG. 2 is a block diagram showing the circuit configuration inside the sequence calculation circuit of FIG.
This figure is a block diagram showing the MOV command applied to the sequence control device of FIG. 1. In the figure, 1... central processing unit (CPLJ), 2...
... Clock generator, 3... Bus controller, 4... Address latch, 5... Address decoder, 6... l10 (input/output) interface, 7...
Memory,...Sequence calculation circuit, 9.10...Bidirectional buffer, 11...Instruction decoder, 12...
Arithmetic unit, 13...Arithmetic result holding register, 14...
ANB/ORB stack, 15... mask controller, 16... calculation data selection multiplexer, 17.
. . . data holding register, 18 . . . data swap multiplexer, 19 . . . timing generator. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
マイクロプロセツサとビット処理専用回路等から成る中
央演算処理回路により演算処理するように構成したシー
ケンス制御装置。A sequence control device configured so that data processing, sequence instruction decoding, etc. are performed by a central processing circuit consisting of a 16-bit microprocessor, a circuit dedicated to bit processing, etc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2525983U JPS59134803U (en) | 1983-02-23 | 1983-02-23 | Sequence control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2525983U JPS59134803U (en) | 1983-02-23 | 1983-02-23 | Sequence control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59134803U true JPS59134803U (en) | 1984-09-08 |
Family
ID=30156249
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2525983U Pending JPS59134803U (en) | 1983-02-23 | 1983-02-23 | Sequence control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59134803U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57136206A (en) * | 1981-02-17 | 1982-08-23 | Toshiba Corp | Sequence controller |
| JPS57168347A (en) * | 1981-04-09 | 1982-10-16 | Toshiba Corp | Computer system |
-
1983
- 1983-02-23 JP JP2525983U patent/JPS59134803U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS57136206A (en) * | 1981-02-17 | 1982-08-23 | Toshiba Corp | Sequence controller |
| JPS57168347A (en) * | 1981-04-09 | 1982-10-16 | Toshiba Corp | Computer system |
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