JPH0466646U - - Google Patents

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Publication number
JPH0466646U
JPH0466646U JP10733590U JP10733590U JPH0466646U JP H0466646 U JPH0466646 U JP H0466646U JP 10733590 U JP10733590 U JP 10733590U JP 10733590 U JP10733590 U JP 10733590U JP H0466646 U JPH0466646 U JP H0466646U
Authority
JP
Japan
Prior art keywords
input
outputting
systems
output devices
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10733590U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10733590U priority Critical patent/JPH0466646U/ja
Publication of JPH0466646U publication Critical patent/JPH0466646U/ja
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク図、第２
図は従来のエミユレーシヨンＣＰＵを使用したマ
イクロコンピユータ用開発支援装置の一例のブロ
ツク図、第３図は第２図の制御信号発生回路と外
部制御信号発生回路の回路図である。 １００……ＣＰＵ、１０１，１０２……入出力
装置、１１０……命令解読部、１１１……データ
バス制御部、１１２……アドレスバス制御部、１
１３，１１４……直接制御信号生成部、１２０…
…データバス、１３０……アドレスバス、１４０
……入出力装置１０１の制御信号、１５０……入
出力装置１０２の制御信号。 Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of an example of a development support device for a microcomputer using a conventional emulation CPU, and FIG. 3 is a circuit diagram of the control signal generation circuit and external control signal generation circuit of FIG. 2. 100...CPU, 101, 102...I/O device, 110...Instruction decoding unit, 111...Data bus control unit, 112...Address bus control unit, 1
13, 114...direct control signal generation section, 120...
...Data bus, 130...Address bus, 140
... Control signal for the input/output device 101, 150... Control signal for the input/output device 102.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部のメモリ等の二系統の入出力装置との間で
入出力を行なうための制御出力端子を有するマイ
クロコンピユータのエミユレーシヨンＣＰＵにお
いて、前記二系統の入出力装置との間をそれぞれ
直接入出力するための直接制御信号生成回路を内
蔵する事を特徴とするエミユレーシヨンＣＰＵ。 In an emulation CPU of a microcomputer, which has a control output terminal for inputting and outputting between two systems of input/output devices such as external memory, for directly inputting and outputting between the two systems of input/output devices, respectively. An emulation CPU characterized by having a built-in direct control signal generation circuit.
JP10733590U 1990-10-12 1990-10-12 Pending JPH0466646U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10733590U JPH0466646U (en) 1990-10-12 1990-10-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10733590U JPH0466646U (en) 1990-10-12 1990-10-12

Publications (1)

Publication Number Publication Date
JPH0466646U true JPH0466646U (en) 1992-06-12

Family

ID=31853799

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10733590U Pending JPH0466646U (en) 1990-10-12 1990-10-12

Country Status (1)

Country Link
JP (1) JPH0466646U (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0224732A (en) * 1988-07-13 1990-01-26 Nec Corp Microcomputer
JPH0277848A (en) * 1988-06-10 1990-03-16 Nec Corp Microcomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0277848A (en) * 1988-06-10 1990-03-16 Nec Corp Microcomputer
JPH0224732A (en) * 1988-07-13 1990-01-26 Nec Corp Microcomputer

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