JPH0224732A - Microcomputer - Google Patents

Abstract

PURPOSE:To make access to an emulation memory without setting up a port for the access and to improve access speed by adding a specific instruction for executing data access to the emulation memory and a user memory to an everchip during the operation of a specific interruption function (SV) for program developing supporting tool. CONSTITUTION:The I/O port of a microcomputer 9 in the everchip 310 has an external memory expanding function in addition to its I/O port function. TA specific transfer instruction for making data access to an emulation memory 120 and a user memory 130 is newly set up in the everchip 310. A CPU 110-1 outputs an SIF signal 110-8 to be outputted synchronously with the specific transfer instruction and a PSEL signal 110-14 for specifying whether a 1st OPRT 110-6 is to be used as an I/O port or not. Consequently, a bus control unit 110-5 is connected to address buses 160, 170 for making access to the memory 120 or 130.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program development microcomputer for developing a program to be executed on a microcomputer.

[Conventional technology]

Generally, when developing a program that runs on a microcomputer, the program execution operation can be performed in the same way as the target microcomputer, and there is a function to interrupt program execution at a certain address (hereinafter referred to as a break function), and a A program development support tool (hereinafter referred to as ICE) is used that has functions that allow easy depacking of programs, such as functions for reading and changing the memory contents of the program. In order to realize the above functions on the ICE, in addition to the functions of a normal microcomputer, output of an internal status signal representing the internal operation of the microcomputer (instruction code fetch, data access, etc.),
A microcomputer for program development (hereinafter referred to as an Evachip) is used, which is equipped with functions such as a special interrupt function (hereinafter referred to as 87 interrupt).

One of the microcomputers targeted by this Evachip is a one-chip microcomputer, which has internal memory and many input/output ports. One of the input/output ports also has the function of operating as an input/output terminal for bus and control signals when memory is expanded outside the microcomputer.

The configuration of an ICE using a conventional Eva chip will be explained using the block diagram shown in FIG. The ICE shown in FIG. 5 includes an evaluation chip 310, an emulation memory 320, a user memory 330, an alternate memory 340, a break function circuit 350, a decode circuit 360, a chip select circuit 370, and an I10 emulation circuit 38.
Consists of 0.

The emulation memory 320 corresponds to the memory included inside the microcomputer to which the Eva chip 310 is intended. Further, the user memory 330 corresponds to a memory located outside the microcomputer to which the Evachip 310 is intended. The above two memories are used by a program developed by a user (hereinafter referred to as a user program) as a program and data area.

Since the storage address of the monitor program and data area during the 87 interrupt processing overlaps with the program and data area of the user program, the alternate memory address 340 is used as the storage area.

The break function circuit 350 receives a status signal 3, which will be described later.
It has a function of monitoring 01, LAD bus 390, and EALE 311 and activating the 87 interrupt request signal 302 output to the EV chip 310 when an instruction at a predetermined address is executed.

The decoding circuit 360 receives a status signal 301 which will be described later.
It has a function of monitoring the data access signal 303 and outputting 1 to the data access signal 303 while the evaluation chip 310 is executing a memory access bus cycle.

The chip select circuit 370 receives the data access signal 30
3 and monitors the LAD bus 390, EALE 311, first output port 304, and SVMOD signal 306, which will be described later.
Alternate memory 340 and emulation memory 3
20 and I10 emulation circuit 380, the first chip select signal 307 and the second chip select signal 30
8 and a third chip select signal 309 are output. When the chip select signal is 1, the target memory can perform data access. FIG. 6A shows the chip select circuit 3.
70 configuration is shown. The decoder 379 is a first A decoder, which will be described later.
The D bus 390 is latched at the timing of the EALE signal 311, and if the value is in the user memory 330 area, O is output, and if the value is in the emulation memory 320 area, 1 is output to the decoder output 381. FIG. 6B shows the truth value of this circuit.

The I10 emulation circuit 380 has a function of emulating the input/output ports of the target microcomputer. The input/output port also serves as an external memory expansion terminal. Therefore, the PSEL signal 32 described later
Depending on the value of 1, it is possible to specify whether the second AD bus 400 is used as a bus or as an input/output port. When used as an external memory expansion terminal, the LAD bus 390 and the second AD bus 400, the EALE signal 311 and the ALE signal 314, the ERD signal 312 and the RD signal 315, and the EWR signal 313 and the WR signal 316 are connected.

The evaluation chip 310 performs instruction execution processing, and outputs an SVMOD signal 306 that outputs 1 during an 87 interrupt, and an I10
A PSEL signal 321 that specifies whether the second AD bus 400 of the emulation circuit 380 is used as a bus or an input/output port, a status signal 301 that indicates the current internal state of the evaluation chip 310, and a first AD bus 400 that can be set by a program. Output port 304. The LAD bus 390 is a bus for exchanging addresses and data during memory access. Also, an EALE signal 31 that specifies the address output timing on the first AD bus 390.
1, an ERD signal 312 and an EWR signal 313 specifying memory read and write timings are also output.

The first AD bus 390 is connected to the alternate memory 340 and the emulation memory 320.

The emulator circuit 380 and the evaluation chip 310 are connected. The second AD bus 400 connects the user memory 330 and
10 emulation circuit 380 is connected.

Next, using the timing charts in Figures 7A to E,
The memory access operation during ICE operation will be explained. In these figures, tl-t2. t3-t4. t4-t5
indicates the timing of instruction food fetch, and t2-t3 indicates the timing of data access. Therefore, the data access signal 303 is 1 during the period t2-t3.

Also, regarding the timing of data access, a solid line indicates reading from memory, and a broken line indicates writing to memory.

FIG. 7A is a timing chart of memory access to emulation memory 320 when a user program is being executed, and FIG. 7B is a timing chart of memory access to user memory 330 when a user program is being executed. 87 interrupt processing is not performed, the SVMOD signal 306
is 0. Therefore, the first chip select signal 307 becomes 0. If the memory access address is an area of the emulator 3 non-memory 320, the second chip select signal 308 becomes 1 and the emulation memory 320 becomes memory accessible. If the memory access address is an area of the user memory 330, the third chip select signal 309 becomes 1 and the user memory 330
30 becomes memory accessible. The evaluation chip 310 includes an emulation memory 320 and a user memory 33.
0, performs instruction code fetch and data access processing, and executes the user program.

FIG. 7C is a timing chart when the monitor program stored in the alternate memory 340 is fetching instructions and accessing data to the alternate memory 340. Since the 87 interrupt is being processed, the SVMOD signal 306 is 1. The first output port 304 is set to O. From FIG. 6B, the first chip select signal 307 becomes 1, the second chip select signal 308 and the third chip select signal 309 become 0, and the alternate memory 340 becomes memory accessible. The evaluation chip 310 performs instruction code fetch and data access processing for the alternate memory 340, and executes the monitor program.

Figure 7 shows when the monitor program accesses data to the emulation memory 320 during 87 interrupt processing, and Figure 7 E shows when the monitor program accesses data to the emulation memory 330 during 87 interrupt processing. This is a timing chart. 8
7 interrupt processing is in progress, so the SVMOD signal 306 is 1. At the time tl-t2, the data access signal 303 becomes O, so the first chip select signal 307
is 1, the second chip select signal 308 is 0, the third chip select signal 309 is 0, and the alternate memory 3
40 becomes accessible, and the alternate memory 340
An instruction code fetch is performed from there. The monitor program causes the first output port 304 to be set to 1 at the time of tll.
After being set to 0, when data access is performed from t2 to t3, the first chip select signal 307 becomes 0.

If the data access address is an area of the emulation memory 320, the second chip select signal 308 is set to 1.
As a result, emulation memory 320 becomes accessible and data access is performed from emulation memory 330.

If the data access address is an area of the user memory 330, the third chip select signal 309 becomes 1,
RD signal 315 and WR signal 316 in user memory 330
is output and data access is performed from the user memory 330. At time t3, the data access signal 303 is 0.
Therefore, the first chip select signal 307 is 1, the second chip select signal 307 is
The chip select signal 308 becomes 0, the third chip select signal 309 becomes O, and the alternate memory 340 becomes accessible, t3-t4. At t4-t5, an instruction code is fetched from the alternate memory 340.

[Problem to be solved by the invention]

In the ICE using the conventional Eva chip described above, in order to access data to the emulation memory and user memory during 87 interrupt processing, in addition to the memory access instruction, an instruction to set the output port is executed before and after the instruction. This makes it impossible for the monitor program to process the emulation memory and user memory at high speed.

Furthermore, in order to switch between the alternate memory, emulation memory, and user memory, it is necessary to use one terminal of each port, and it is necessary to impose restrictions on the ports that can be used by the user.

Furthermore, in order to create a chip select signal that switches between alternate memory, emulation memory, and user memory, there is a status signal decoding circuit outside the evaluation chip, a chip select circuit that creates a chip select signal, and a bus select circuit that switches the bus connected to the user memory. There is a drawback that an additional circuit such as a circuit is required, which increases the number of parts of the ICE.

[Means to solve the problem]

A microcomputer according to the present invention includes an instruction execution means for executing instructions, a plurality of input/output means for inputting/outputting data to/from an external device, an output terminal, and a plurality of input/output means for inputting/outputting data to/from an external device. The apparatus includes a selection section that controls the state of the output terminal in synchronization with the input/output processing and selects one of the plurality of input/output means in synchronization with the state of the output terminal.

That is, compared to the conventional Eva chip, the Eva chip of the present invention has a special instruction added for accessing data to the emulation memory and user memory during 87 interrupt processing, and the special instruction allows access to the emulation memory and user memory. On the other hand, at the timing of data access, a signal that becomes 0, for example, is generated within the EV chip in synchronization with that timing, and is output to the outside as a chip select signal. Furthermore, the bus control unit performs a bus switching operation in synchronization with the signal.

〔Example〕

Next, the configuration of an ICE using an Eva chip, which is a first embodiment of the present invention, will be explained using the block diagram of FIG.

In the evaluation chip of this embodiment, a special transfer instruction for accessing data to the emulation memory and user memory during 87 interrupt processing is newly set.
A signal that becomes 0 in synchronization with the timing of data access to the emulation and user memory according to the special command is created within the EV chip, and is output to the outside as a signal for discrimination.

In addition, the bus control unit performs bus switching processing in synchronization with the signal.

That is, the ICE shown in FIG. 1 is composed of an evaluation chip 110, an emulation memory 120, a user memory 130, an alternate memory 140, and a break function circuit 150 based on the present invention. Of these, the emulation memory 120 and the user memory 130
, alternate memory 140, break function circuit 150
The configuration and functions of the device are the same as those described in the conventional example, so detailed explanation will be omitted.

The evaluation chip 110 includes a CPU section 110-1, a bus control unit 110-5, and a first internal bus 110-5 that connects the CPU section 110-1 and the bus control unit 110-5.
4, the first PO'RT 110-6, the internal bus 2 110-7 connecting the bus control unit 110-5 and the first PORTIIO-6, the NAND game) 110-2, and the A
It is composed of an ND gate 110-3. Evachip 310
In addition to the input/output boat function, the microcomputer's input/output board that is the subject of this paper has an external memory expansion function. In addition to executing instruction processing, the CPU section 110-1 outputs l during the 87 interrupt and outputs the SVMOD signal 110-1.
0, a data access signal 110-9 that outputs 1 in synchronization with the data access bus cycle, and the CPU section 11.
An SIF signal 110-8 in which 0-1 outputs 1 in synchronization with the execution of a special transfer instruction based on the present invention, and a first F signal to be described later.
Each outputs a PSEL signal 110-14 specifying whether ORTIIO-6 is used as an input/output port.

bus control unit) 110-5 is an ALT signal 1 which will be described later.
17 is 00:00, upon receiving a memory access request from the CPU unit 110-1, a determination process is performed on the address of the memory access, and if the access address is an area of the emulation memory 120, the memory is sent to the first AD bus 160. It has the function of causing memory access to the second AD bus 170 if it is an area of the user memory 130. When the ALT signal 117, which will be described later, is 1, a memory access is made to the LAD bus 160. Moreover, the bus control unit 1.10-5
EALE signal 111 that specifies address output timing on AD bus 160, ERD signal 112 and EWR signal 113 that specifies memory read and write timing.
, an IALE signal 110-11 that specifies address output timing on the second internal bus 110-7, and an IRD signal 110 that specifies memory read and write timing.
-12 and IWR signals 110-13 are also output, respectively.

The first FORTI 10-6 has an input/output port function and an external memory expansion function, and the PSEL signal 110-1
The value of 4 controls whether the second AD bus 170 is used as an input/output port or as a bus. N
AND gate) 110-2 and AND gate 110-3 receive SVMOD signal 1 output from CPU section 11O-1.
10-10, data access signal 110-9, and SI
The F signal 110-8 is used to generate an ALT signal 117 for controlling the bus control unit 110-5, alternate memory 140, and emulation memory 120. The Eva chip 110 also outputs a status signal 118 indicating the current internal state of the Eva chip 110.

The alternate memory 140 and the third emulator memory 120 are connected to the evaluation chip 110 by a first AD bus 160. The user memory 130 is the Eva chip 11
0 through a second AD bus 170.

Next, using the timing charts in Figure 2 A to E,
The memory access operation during ICE operation will be explained. In these figures, tl-t2. t3-t4. t4-t5
indicates the instruction code fetch timing, t2-t3 indicates the data access timing, and t2-t
The data access signal 110-9 is 1 during the 3 periods. Also, regarding the timing of data access, a solid line indicates reading from memory, and a broken line indicates writing to memory.

FIG. 2A is a timing chart of memory access to the emulation memory 120 while a user program is being executed, and FIG. 2B is a timing chart of memory access to the user memory 130. In this example, 87 interrupt processing is not performed, so the SVMOD signal 110-10 is 0 and the ALT signal 117
also becomes 0.

Since the ALT signal 117 is 0, the bus control unit 110-5 controlled by the ALT signal 117 tosses the emulation memory 120 as a reference object. Evachip 11
0 is emulation memory 120 and user memory 1
30 to perform instruction food fetch and data access processing and execute the user program.

FIG. 2C is a timing chart when the monitor program fetches an instruction code and accesses data from the alternate memory 140 during 87 interrupt processing. Note that the SVMOD signal 110-1.0 is 1 while the 87 interrupt is being processed. Also, since no special input/output instructions are used, the SIF signal 110-8 is 0.

From the values of the two signals, the ALT signal 117 becomes 1,
(bus control unit controlled by ALT signal 117)
110-5 selects the third LAD bus 160, and the alternate memory 140 becomes memory accessible.

The evaluation chip 110 performs instruction code fetch and data access processing on the alternate memory 140, and executes the monitor program.

The second figure is a timing chart when the monitor program accesses data to the emulation memory 120 during 87 interrupt processing, and the second figure E is a timing chart when the monitor program accesses data to the user memory 130 during 87 interrupt processing. Since the 87 interrupt is being processed, the SVMOD signal 11
0-10)*1. Since the timing of tl-t2 is the instruction code fetch timing, the data access signal 110-9 is O, so the ALT signal 117 becomes 1, and the bus control unit 110-5 controlled by the ALT signal 117, - Ritsudai LAD Bus 1
60 is selected, and the alternate memory 140 becomes the target of memory access. The timing of t2-t3 indicates the timing of data access by the special transfer command, and the SIF signal 110-8 becomes 1, the data access signal 110-9 becomes 1, and the ALT signal 117 becomes 0. Therefore, AL
Bus control unit 11 controlled by T signal 117
0-5, since the target of memory access is the emulation memory 120 in the second diagram, the LAD bus 160 is selected and the emulation memory 120 becomes the target of memory access. In addition, in the case of FIG. 2E, the target is the user memory 130, so the Eva chip 110 is
Perform data access to 0. t3-t4. t
4-t5 timing is data access signal 110-9
is 0, so the ALT signal 117 becomes 1 and A
Bus control unit controlled by LT signal 117, )
110-5 selects the first AD bus 160, and the alternate memory 140 becomes the object of memory access. For the Eva chip 110 and the alternate memory 140,
Perform instruction code fetch.

Next, the ICE using the Eva chip, which is the second embodiment of the present invention, has a special instruction 1 that switches the data access target from the alternate memory to the emulation memory and the user memory, and a special command 1 that switches the data access target from the emulation memory and the user memory. It has a special instruction 2 for switching from memory to alternate memory.

The ICE shown in FIG.
0, an emulation memory 220, a user memory 230, an alternate memory 240, and a break function circuit 250. Of these, the configurations and functions of the emulation memory 220, user memory 230, alternate memory 240, and break function circuit 250 are the same as those described in the conventional example, and therefore detailed explanations will be omitted.

The evaluation chip 210 includes a CPU section 210-1, a bus control unit 210-5, and a first internal bus 210-5 that connects the CPU section 210-1 and the bus control unit 210-5.
4, the first PO'RT210-6, the second internal bus 210-7 connecting the bus control unit 210-5 and the first PORT210-6, the R8FF210-15, and the NAN
It has a D gate 210-2 and an AND gate 210-3. Among these, the bus control unit 210-5,
The first internal bus 210-4 as a signal line and the FORTI 2
Since the bus 10-6 and the second internal bus 210-7 are the same as those described in the first embodiment, detailed description thereof will be omitted. The CPU section 210-1 performs instruction execution processing, and outputs an SvMOD signal 210-10 that outputs 1 during an 87 interrupt;
When the memory access request of unit 210-1 is data access, a data access signal 210-9 outputs 1 in synchronization with the bus cycle, and an FSET signal outputs a single pulse in synchronization with the execution of special instruction 1. 210-1
6, FCLR signal 210-17 which outputs a single pulse in synchronization with the execution of special instruction 2, and 1st FORT 2.
P to specify whether to use 10-6 as an input/output port
Outputs SEL signal 210-14. R3-FF210
-15 and NAND gate 210-2 and AND gate 21
〇-3 is the SvMO output from the CPU section 210-1
D signal 210-10 and data access signal 210-9
, FSET signal 210-16, and FCLR signal 210
-17 is used to connect the bus control unit 210-5, alternate memory 240 and emulation memory 220.
The ALT signal 217 is generated to control the ALT signal 217. The Eva chip 210 also outputs a status signal 218 indicating the current internal state of the Eva chip 210.

Next, using the timing charts in Figure 4 A to E,
The memory access operation during ICE operation will be explained. In these figures, tl-t2. t2-t3. t4-t5
indicates the timing of instruction code fetch, and t3-t4 indicates the timing of data access. Therefore, the data access signal 210-9 is 1 during the period t3-t4.
It becomes. Also, regarding the timing of data access, a solid line indicates reading from memory, and a broken line indicates writing to memory.

The timing charts in FIGS. 4A and 4B are timing charts for memory access to the emulation memory 220 and the user memory 230 when a user program is being executed. This operation is the same as in the previous embodiment, so a detailed explanation will be omitted.

The timing chart in FIG. 4C is a timing chart when the monitor program fetches an instruction code and accesses data from the alternate memory 240 during the 87 interrupt processing. Since the 87 interrupt is being processed, the SVMOD signal 210-10 is 1, but the special instruction 1 is not used, so the R8-FF 21
0-15 are in the RESET state. Based on the values of the two signals, the ALT signal 217 becomes 1, and the ALT signal 2
The bus control unit 210-5 controlled by the bus control unit 210-5 selects the third LAD bus 260, and the alternate memory 240 becomes the target of memory access. Evachip 21
0 performs instruction code fetch and data access processing for the alternate memory 240 and executes the monitor program.

The timing chart in Figure 4 shows when the monitor program accesses data from the emulation memory 220 during 87 interrupt processing, and the timing chart in Figure 4 E shows when the monitor program accesses data from the user memory 230 during 87 interrupt processing. This is a timing chart. Since the 87 interrupt is being processed, the SVMOD signal 210-10 is 1. tl-t2. Since the timing of t2-t3 is the instruction code fetch timing, the data access signal 210-9 is 0, so A
When the LT signal 217 becomes 1, the bus control unit 210-5 controlled by the ALT signal 217 outputs -LAD
Bus 260 is selected and alternate memory 240 becomes the target of memory access. The evaluation chip 210 fetches an instruction code from the alternate memory 240. The timing of t3-t4 indicates the timing of data access to the emulation memory 220. At the time of tll, FSE is activated by executing special instruction 1.
A single pulse is output to the T signal 210-16, and R3
-FF210-15 is set. At t3-t4, which is the data access timing, R8-FF 210
-15 is set state, data access signal 210-9
is 1, so the ALT signal 217 becomes 0 and A
Bus control unit controlled by LT signal 217)2
10-5 performs a bus switching operation based on a memory access address.

In the case of the fourth diagram, the target is the emulation memory 220
Therefore, the second AD bus 270 is selected and the ALT signal 217 is
Since 0 is 1, the emulation memory 220 becomes the target of memory access. In the case of FIG. 4E, the target is the user memory 230, so the second AD bus 270 is selected and the Eva chip 210 accesses data to the user memory 230. R3-FF210-15 is t41
At the point in time, it is RESETed by special command 2, and the ALT signal 217 becomes 1.

From now on, data access will be performed using the alternate memory 240.
is carried out against Since the data access signal 210-9 is 0 at the timing of t4-t5, the ALT
Since the signal 217 becomes 1, the bus control unit 210-5 controlled by the ALT signal 217 selects the -regular LAD bus 260, and since the ALT signal 217 is 1, the alternate memory 240 becomes the target of memory access. The evaluation chip 210 performs an instruction food fetch to the alternate memory 240.

〔Effect of the invention〕

As explained above, the present invention adds a special instruction to the evaluation chip to access data in the emulation memory and user memory during 87 interrupt processing, and also provides a chip select function that changes the output value in synchronization with the data access reference bus cycle. By adding an output terminal, the following effects can be obtained.

■ Since the chip select signal that switches between emulation memory, user memory, and alternate memory is supplied from inside the evaluation chip, there is no need to add an external circuit to create a chip select signal, and also switches the bus that accesses the user memory. There is no need to add a bus select circuit for this purpose, and the number of ICE parts can be reduced.

■ Unlike ICE using conventional Eva chips, there is no need to set each port to be operated by software one by one in order to access emulation memory and user memory while the monitor program is running. You can increase the speed.

(2) Furthermore, data access to the emulation memory and user memory during 87 interrupt processing can be executed with one instruction, thus speeding up processing from the monitor program to the emulation memory and user memory.

■ Access to emulation memory and user memory during 87 interrupts can be executed with one instruction.
The procedure for accessing the emulation memory and user memory during the monitor program can be simplified.

■ It is faster to use special instructions to switch internal signals of the Eva-chip than to set output port values and switch memory access targets. and user memory, it can be executed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an ICE using an EV chip according to an embodiment of the present invention, FIGS. 2 A to E are timing charts of the operation of the EV chip used in the embodiment of FIG. I using the Evachip according to the embodiment of
A block diagram of the CE, FIGS. 4A to 4E are timing charts of the operation of the EV chip used in the embodiment in FIG. 3, FIG. 5 is a block diagram of an ICE using a conventional EV chip, and FIGS. B is a circuit diagram and a truth value diagram of the chip select circuit shown in FIG. 5, respectively, and FIGS. 7A to 7E are timing charts of the operation of the EV chip used in the conventional example. Evachip...110. ．． 210,310,C
PU section...110-1, 210-1, NAND
Gate...110-2, 210-2, 374,
AND gate...110-3, 210-3, 3
75, Internal bust...110-4.210-4,
Bus control unit...110-5.210-5
, PORTl...110-6, 210-6, Inner bus 2...110-7, 210-7, SIF
Signal...110-8, data access signal...
...l'l O-9,210-9,303,SVM
OD signal ----110-10゜210-10,3
06, IALE signal...110-11,210
-11, IRD signal...11〇-12,210
-12, IRD signal 110-13゜210-13, PS
EL signal...110-14°210-14,3
21, EALE signal...111°211.31
1. ERD signal...112,212°312,
EWR signal -113,213,303, ALE signal...114,214,314, RD double signal
...115,215,315, WR double signal--
・116.216,316, ALT signal...1
17°217, status signal...118,2
18゜301.87 Interrupt request signal...11
9,219°302, Emulation memory...
Self...120°220.320, User memory...
...130,230°330, alternate memory...
...140,240°340, break function circuit・
...150,250°350, AD bust...
・・・160,260,390, AD Babasu...
170,270,400, R8-FF...21
0-15, FSET signal...21〇-16, F
CL'R signal...210-17, output port...304, chip select signal 1...
307, Chip select signal 2...308, Chip select signal 3...309, Decode circuit...360, Chip select circuit...
370. NOR game) ---376,377, IN
VERTER-・・・378, I10 emulator)
Circuit...380°Representative Patent Attorney Hara Uchi
Sound 2 figure A 2nd □F3 figure C Gu2 field D IZ plane E 4th flash A Difference 4 circle B $4 ′vMc Mocha 4 Concave first fork E Mochi A Mocha picture 5 Sheep concave broom A C Kaya blade E

Claims (1)

[Claims] A command execution means for executing commands, a plurality of input/output means for performing data input/output processing for external devices, a terminal, and synchronization with input/output processing by commands for performing data transfer processing for external devices. to control the state of the terminal;
A microcomputer comprising: a selection section that selects one input/output means from the plurality of input/output means in synchronization with the state of the terminal.