JPS6266345U - - Google Patents
Info
- Publication number
- JPS6266345U JPS6266345U JP15647385U JP15647385U JPS6266345U JP S6266345 U JPS6266345 U JP S6266345U JP 15647385 U JP15647385 U JP 15647385U JP 15647385 U JP15647385 U JP 15647385U JP S6266345 U JPS6266345 U JP S6266345U
- Authority
- JP
- Japan
- Prior art keywords
- data processing
- processing unit
- microprogram
- additional data
- processing device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例によるマイクロプ
ログラム制御方式のデータ処理装置を示すブロツ
ク図、第２図は従来のマイクロプログラム制御方
式のデータ処理装置を示すブロツク図である。
１Ｂは付加データ処理部用制御メモリ、３は基
本データ処理部、３Ａは付加データ処理部、５は
クロツク信号、６はデコーダ（第１手段）、７は
ＡＮＤ回路（第２手段）である。なお、図中、同
一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing a microprogram control type data processing apparatus according to an embodiment of this invention, and FIG. 2 is a block diagram showing a conventional microprogram control type data processing apparatus. 1B is a control memory for an additional data processing section, 3 is a basic data processing section, 3A is an additional data processing section, 5 is a clock signal, 6 is a decoder (first means), and 7 is an AND circuit (second means). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
部にオプシヨンとして付加された少なくとも１個
の付加データ処理部を有するデータ処理装置にお
いて、前記基本データ処理部中の制御メモリの全
アドレス空間の一部に相当するアドレス空間があ
る付加データ処理部用制御メモリと、この付加デ
ータ処理部用制御メモリ内に格納されたマイクロ
プログラムのアドレスをデコードし、このマイク
ロプログラムが有効か無効かを判定する第１手段
と、この第１手段の出力によつて付加データ処理
部に対するマイクロプログラムの実行クロツクを
制御する第２手段とを備えたことを特徴とするデ
ータ処理装置。 (2) 第１手段はデコーダよりなり、第２手段は
ＡＮＤ回路よりなることを特徴とする実用新案登
録請求の範囲第１項記載のデータ処理装置。[Claims for Utility Model Registration] (1) In a data processing device having a basic data processing unit and at least one additional data processing unit added as an option to the basic data processing unit, control in the basic data processing unit The control memory for the additional data processing unit has an address space corresponding to a part of the total address space of the memory, and the address of the microprogram stored in this control memory for the additional data processing unit is decoded, and this microprogram is validated. 1. A data processing device comprising: a first means for determining whether a microprogram is invalid; and a second means for controlling an execution clock of a microprogram for an additional data processing section based on the output of the first means. (2) The data processing device according to claim 1, wherein the first means comprises a decoder and the second means comprises an AND circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15647385U JPS6266345U (en) | 1985-10-15 | 1985-10-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15647385U JPS6266345U (en) | 1985-10-15 | 1985-10-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6266345U true JPS6266345U (en) | 1987-04-24 |
Family
ID=31078122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15647385U Pending JPS6266345U (en) | 1985-10-15 | 1985-10-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6266345U (en) |
-
1985
- 1985-10-15 JP JP15647385U patent/JPS6266345U/ja active Pending
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