JPS6165548U - - Google Patents
Info
- Publication number
- JPS6165548U JPS6165548U JP14747784U JP14747784U JPS6165548U JP S6165548 U JPS6165548 U JP S6165548U JP 14747784 U JP14747784 U JP 14747784U JP 14747784 U JP14747784 U JP 14747784U JP S6165548 U JPS6165548 U JP S6165548U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- central processing
- instruction
- memory
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 6
Description
第１図はこの考案の一実施例の構成を示す回路
図、第２図は第１図に示すオペレーシヨンコード
検出回路とメモリ制御回路の具体的構成の一例を
示す回路図、第３図は第２の動作を説明するため
のタイミングチヤート、第４図は第１図のメモリ
マツプを示す図、第５図は従来のメモリ拡張装置
を示す回路図、第６図は第５図のメモリマツプを
示す図である。
２１……ＣＰＵ、２２，２３……メモリ、２４
……オペレーシヨンコード検出回路、２５……メ
モリ制御回路。
FIG. 1 is a circuit diagram showing the configuration of an embodiment of this invention, FIG. 2 is a circuit diagram showing an example of a specific configuration of the operation code detection circuit and memory control circuit shown in FIG. 1, and FIG. A timing chart for explaining the second operation, FIG. 4 is a diagram showing the memory map of FIG. 1, FIG. 5 is a circuit diagram showing a conventional memory expansion device, and FIG. 6 is a diagram showing the memory map of FIG. 5. It is a diagram. 21...CPU, 22, 23...Memory, 24
...Operation code detection circuit, 25...Memory control circuit.
Claims (1)
否を検出する命令検出手段と、 この命令検出手段によつて上記中央演算処理装
置が上記特定の命令を読み込んだとの検出出力が
あつたとき、上記中央演算処理装置のプログラム
が格納されているメモリ空間とは別のメモリ空間
をアクセスするメモリ制御手段とを具備したメモ
リ拡張装置。[Claims for Utility Model Registration] Instruction detection means for detecting whether or not the central processing unit has read a specific instruction; and the instruction detection means detects whether the central processing unit has read the specific instruction. A memory expansion device comprising memory control means for accessing a memory space different from a memory space in which a program of the central processing unit is stored when a detection output is received.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14747784U JPS6165548U (en) | 1984-09-29 | 1984-09-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14747784U JPS6165548U (en) | 1984-09-29 | 1984-09-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6165548U true JPS6165548U (en) | 1986-05-06 |
Family
ID=30705703
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14747784U Pending JPS6165548U (en) | 1984-09-29 | 1984-09-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6165548U (en) |
-
1984
- 1984-09-29 JP JP14747784U patent/JPS6165548U/ja active Pending
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