JPH0474342U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional embodiment. 1 is the CPU, 2 is the main memory, 3 is the read signal,
4 is a data bus, 5 is an address bus, 6 is an invalid data detection circuit, 7 is an error signal, 9 is an error signal holding circuit, 10 is an emergency processing memory, 11 is an emergency data bus, 13 is a data selector, 15 is an address counter , 16 is the address. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] The CPU that executes calculations, the main memory that stores programs, the emergency processing memory that stores programs for emergency processing, and the address of the emergency processing memory as CP.
An address counter that counts based on the memory read signal output from the U, an invalid data detection circuit that determines whether the data output from the main memory is correct or incorrect based on the timing of the memory read signal from the CPU, and invalid data. An error signal holding circuit that stores the error signal output by the detection circuit until the error processing is completed; data that switches program transfer from the main memory to the emergency processing memory to the CPU in response to a memory switching signal output from the error signal holding circuit; It consists of a selector, and when an error is detected in the data output from the main memory, the program transfer to the CPU is switched from the main memory to the emergency processing memory by the data selector.
An error processing circuit characterized in that an emergency processing program is sequentially transferred to a CPU while advancing an address counter for an emergency processing memory at the timing of a memory read signal.